參數(shù)資料
型號: IDT88P8344BHI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 6/98頁
文件大小: 0K
描述: IC SPI3-SPI4 EXCHANGE 820-PBGA
標準包裝: 24
系列: *
其它名稱: 88P8344BHI
14
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Figure 3. Link mode SPI-3 ingress interface
IDT88P8344
(LINK MODE)
PHY
I_FCLK
I_MOD[1:0]
6370 drw25
I_RSX
I_ENB
I_EOP
I_SOP
RVAL
I_PRTY
I_Data[31:0]
I_ERR
Figure 4. PHY mode SPI-3 ingress interface
byte mode
packet mode
6370 drw26
IDT88P8344
(PHY MODE)
LINK
I_FCLK
I_MOD[1:0]
I_SOP
I_ENB
I_PRTY
I_Data[31:0]
I_ERR
ADDR[7:0]
PTPA
DTPA[3:0]
STPA
I_EOP
I_RSX
SPI-3 ingress Link mode
Refer to [Glossary] for details about the SPI-3 interface.
The PHY pushes data into the device in blocks from 1 up to 256 bytes.
The SPI Exchange provides backpressure for the SPI-3 ingress physical
interface by the I_ENB signal. The I_ENB is asserted when at least one
active LID can not accept data. This feature is enabled by the
BACKPRESSURE_EN flag in the SPI-3 ingress configuration register
(register_offset = 0x01). When the flag is cleared the I_ENB signal will not be
asserted, hence no backpressure can be generated.
SPI-3 ingress PHY mode
The SPI Exchange indicates to the Link layer it has buffer space available
byproperresponsetoeitherLinklayerpolling(packetmode)ordirectindication
on DTPA signals (byte mode). The selection is made by the PACKET flag in
the SPI-3 configuration register.
In packet mode the device responds to polling (by Link layer device)
Inbytemodethedirectstatusindicationislimitedto4addresses(fixedports
[3:0])
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