參數(shù)資料
型號(hào)： IDT88P8344BHI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 51/98頁(yè)
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8344BHI
55
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Primary interrupt enable register (0x2E in the
direct accessed space)
Field
Bits
Length
Initial Value
TIME_BASE_EN
0
1
0
INDIRECT_ACCESS_EN
1
0
Reserved
7:2
6
0
TABLE 47 - SECONDARY INTERRUPT ENABLE
REGISTER(0x2FINTHEDIRECTACCESSEDSPACE)
SPI-4_EN
SPI-4 interrupt enable.
0=Disable SPI-4 interrupt
1=Enable SPI-4 interrupt
SECONDARY_EN
SECONDARY interrupt enable.
0=Disable SECONDARY interrupt
1=Enable SECONDARY interrupt
Secondary interrupt enable register (0x2F in the
direct accessed space)
Thesecondaryinterruptenableregister(0x2Finthedirectaccessedspace)
has read and write access.
The secondary interrupt enable register is used to bitwise enable the
interrupts in the secondary interrupt enable register.
TIME_BASE_EN
Time base expiration interrupt enable.
0=Disable time base event interrupt
1=Enable time base event interrupt
INDIRECT_ACCESS_EN
Indirectaccesscompletioninterruptenable.
0= Disable indirect access completion event interrupt
1=Enable indirect access completion event interrupt
The Primary Interrupt Enable Register (0x2E in the direct accessed space)
has read and write access.
ThePrimaryInterruptEnableRegisterisusedtobitwiseenabletheinterrupts
in the Primary Interrupt Status Register.
MODULE_A_EN
MODULE_A interrupt enable.
0=Disable MODULE_A interrupt
1=Enable MODULE_A interrupt
MODULE_B_EN
MODULE_B interrupt enable.
0=Disable MODULE_B interrupt
1=Enable MODULE_B interrupt
MODULE_C_EN
MODULE_C interrupt enable.
0=Disable MODULE_C interrupt
1=Enable MODULE_C interrupt
MODULE_D_EN
MODULE_D interrupt enable.
0=Disable MODULE_D interrupt
1=Enable MODULE_D interrupt
Field
Bits
Length
Initial Value
MODULE_A_EN
0
1
0
MODULE_B_EN
1
0
MODULE_C_EN
2
1
0
MODULE_D_EN
3
1
0
SPI4_EN
4
1
0
SECONDARY_EN
5
1
0
Reserved
7:6
2
0
TABLE 46 - PRIMARY INTERRUPT ENABLE REGIS-
TER (0x2E IN THE DIRECT ACCESSED SPACE)
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