參數(shù)資料
型號(hào)： IR80C52CXXX-12:RD
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)： 48/101頁(yè)
文件大?。?/td> 3398K
73
8168C-MCU Wireless-02/10
AT86RF212
6.2.2 Handling of Reserved Frame Types
Reserved frame types (as described in section 5.2.3.3) are treated according to bits
AACK_UPLD_RES_FT and AACK_FLTR_RES_FT of register 0x17 (XAH_CTRL_1)
with three options:
1. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 0:
Frames of reserved frame type with correct FCS are indicated by the interrupt IRQ_3
(TRX_END). No further frame filtering is applied on these frames. Interrupt IRQ_5
(AMI) is never generated and no acknowledgment is sent.
2. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 1:
If AACK_FLTR_RES_FT = 1, any frame with a reserved frame type is treated by the
RX_AACK Frame Filter as an IEEE 802.15.4 compliant data frame. This implies the
generation of the interrupt IRQ_5 (AMI) upon address matches.
3. AACK_UPLD_RES_FT = 0
Any frame with a reserved frame type is blocked.
6.2.3 Register Description
Register 0x17 (XAH_CTRL_1):
The XAH_CTRL_1 register is a control register for Extended Operating Mode.
Table 6-7. Register 0x17 (XAH_CTRL_1)
Bit
7
6
5
4
Name
Reserved
CSMA_LBT_MODE
AACK_FLTR_RES_FT
AACK_UPLD_RES_FT
Read/Write
R/W
Reset Value
0
Bit
3
2
1
0
Name
Reserved
AACK_ACK_TIME
AACK_PROM_MODE
Reserved
Read/Write
R
R/W
R
Reset Value
0
Bit 7 – Reserved
Bit 6 – CSMA_LBT_MODE
Refer to section 6.7.3.
Bit 5 – AACK_FLTR_RES_FT
This register bit shall only be set if AACK_UPLD_RES_FT = 1.
If AACK_FLTR_RES_FT = 1, any frame with a reserved frame type is treated by the
RX_AACK Frame Filter as an IEEE 802.15.4 compliant data frame. If
AACK_FLTR_RES_FT = 0, the received reserved frame is only checked for a valid
FCS. See section 6.2.2 for details.
Bit 4 – AACK_UPLD_RES_FT
If AACK_UPLD_RES_FT = 1, received frames which are identified as reserved frames
will not be blocked. See section 6.2.2 for details.
Bit 3 – Reserved
Bit 2 – AACK_ACK_TIME
Refer to sections 5.2.3.3 and 5.2.6.
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