參數(shù)資料
型號(hào)： ISP1181BDGG,112
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝： 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
文件頁數(shù)： 16/70頁
文件大小： 341K
代理商： ISP1181BDGG,112
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
23 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12. Commands and registers
The functions and registers of ISP1181B are accessed via commands, which consist
of a command code followed by optional data bytes (read or write action). An
overview of the available commands and registers is given in Table 13.
A complete access consists of two phases:
1. Command phase: when address bit A0 = 1, the ISP1181B interprets the data on
the lower byte of the bus bits D[7:0] as a command code. Commands without a
data phase are executed immediately.
2. Data phase (optional): when address bit A0 = 0, the ISP1181B transfers the
data on the bus to or from a register or endpoint FIFO. Multi-byte registers are
accessed least signicant byte/word rst.
The following applies for register or FIFO access in 16-bit bus mode:
The upper byte (bits D15 to D8) in command phase or the undened byte in data
phase are ignored.
The access of registers is word-aligned: byte access is not allowed.
If the packet length is odd, the upper byte of the last word in an IN endpoint buffer
is not transmitted to the host. When reading from an OUT endpoint buffer, the
upper byte of the last word must be ignored by the rmware. The packet length is
stored in the rst 2 bytes of the endpoint buffer.
Interrupt Enable
IESUSP
enables output INT to signal the suspend state
IERESM
enables output INT to signal the resume state
Mode
SOFTCT
enables SoftConnect pull-up resistor to USB bus
GOSUSP
a HIGH-to-LOW transition enables the suspend state
Hardware
Conguration
EXTPUL
selects internal (SoftConnect) or external pull-up resistor
WKUPCS
enables wake-up on LOW level of input CS
PWROFF
selects powered-off mode during the suspend state
Unlock
all
sending data AA37H unlocks the internal registers for
writing after a resume
Table 12:
Summary of control bits…continued
Register
Bit
Function
Table 13:
Command and register summary
Name
Destination
Code (Hex)
Initialization commands
Write Control OUT Conguration
Endpoint Conguration Register
endpoint 0 OUT
20
write 1 byte[2]
Write Control IN Conguration
Endpoint Conguration Register
endpoint 0 IN
21
write 1 byte[2]
Write Endpoint n Conguration
(n = 1 to 14)
Endpoint Conguration Register
endpoint 1 to 14
22 to 2F
write 1 byte[2][3]
Read Control OUT Conguration
Endpoint Conguration Register
endpoint 0 OUT
30
read 1 byte[2]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1181BDGG-T 制造商:ST-Ericsson 功能描述:USB Peripheral Controller 48-Pin TSSOP T/R
ISP1181BDGGTM 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1181BPC 制造商:ST-Ericsson 功能描述:Full-Speed Universal Serial Bus Peripheral Controller
ISP1181BS 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER
ISP1181DGG 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device
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