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參數(shù)資料
| 型號： | ISP1181BDGG,112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 7/70頁 |
| 文件大?。?/td> | 341K |
| 代理商： | ISP1181BDGG,112 |
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Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
15 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10. DMA transfer
Direct Memory Access (DMA) is a method to transfer data from one location to
another in a computer system, without intervention of the central processor (CPU).
Many different implementations of DMA exist. The ISP1181B supports two methods:
8237 compatible mode: based on the DMA subsystem of the IBM personal
computers (PC, AT and all its successors and clones); this architecture uses the
Intel 8237 DMA controller and has separate address spaces for memory and I/O
DACK-only mode: based on the DMA implementation in some embedded RISC
processors, which has a single address space for both memory and I/O.
The ISP1181B supports DMA transfer for all 14 congurable endpoints (see Table 4).
Only one endpoint at a time can be selected for DMA transfer. The DMA operation of
the ISP1181B can be interleaved with normal I/O mode access to other endpoints.
The following features are supported:
Single-cycle or burst transfers (up to 16 bytes per cycle)
Programmable transfer direction (read or write)
Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions,
short/empty packet
Programmable signal levels on pins DREQ, DACK and EOT.
10.1 Selecting an endpoint for DMA transfer
The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DMA
Conguration Register, as shown in Table 7. The transfer direction (read or write) is
automatically set by bit EPDIR in the associated ECR, to match the selected endpoint
type (OUT endpoint: read; IN endpoint: write).
Asserting input DACK automatically selects the endpoint specied in the DMA
Conguration Register, regardless of the current endpoint used for I/O mode access.
Table 7:
Endpoint selection for DMA transfer
Endpoint
identier
EPIDX[3:0]
Transfer direction
EPDIR = 0
EPDIR = 1
1
0010
OUT: read
IN: write
2
0011
OUT: read
IN: write
3
0100
OUT: read
IN: write
4
0101
OUT: read
IN: write
5
0110
OUT: read
IN: write
6
0111
OUT: read
IN: write
7
1000
OUT: read
IN: write
8
1001
OUT: read
IN: write
9
1010
OUT: read
IN: write
10
1011
OUT: read
IN: write
11
1100
OUT: read
IN: write
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1181BDGG-T | 制造商:ST-Ericsson 功能描述:USB Peripheral Controller 48-Pin TSSOP T/R |
| ISP1181BDGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181BPC | 制造商:ST-Ericsson 功能描述:Full-Speed Universal Serial Bus Peripheral Controller |
| ISP1181BS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| ISP1181DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
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