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參數(shù)資料
| 型號(hào)： | ISP1181BDGG,112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁(yè)數(shù)： | 25/70頁(yè) |
| 文件大?。?/td> | 341K |
| 代理商： | ISP1181BDGG,112 |
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Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
31 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.7
Write/Read DMA Counter
This command accesses the DMA Counter Register, which consists of 2 bytes. The
bit allocation is given in Table 26. Writing to the register sets the number of bytes for a
DMA transfer. Reading the register returns the number of remaining bytes in the
current transfer. A bus reset will not change the programmed bit values.
The internal DMA counter is automatically reloaded from the DMA Counter Register
when DMA is re-enabled (DMAEN = 1). See Section 12.1.6 for more details.
Code (Hex): F2/F3 — write/read DMA Counter Register
Transaction — write/read 2 bytes
Table 25:
DMA Conguration Register: bit description
Bit
Symbol
Description
15
CNTREN
A logic 1 enables the generation of an EOT condition, when the
DMA Counter Register reaches zero. Bus reset value:
unchanged.
14
SHORTP
A logic 1 enables short/empty packet mode. When receiving
(OUT endpoint) a short/empty packet an EOT condition is
generated. When transmitting (IN endpoint) this bit should be
cleared. Bus reset value: unchanged.
13 to 8
-
reserved
7 to 4
EPDIX[3:0]
Indicates the destination endpoint for DMA, see Table 7.
3
DMAEN
Writing a logic 1 enables DMA transfer, a logic 0 forces the end
of an ongoing DMA transfer. Reading this bit indicates whether
DMA is enabled (0 = DMA stopped, 1 = DMA enabled). This bit
is cleared by a bus reset.
2
-
reserved
1 to 0
BURSTL[1:0]
Selects the DMA burst length:
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes).
Bus reset value: unchanged.
Table 26:
DMA Counter Register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DMACRH[7:0]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
Symbol
DMACRL[7:0]
Reset
00000000
Access
R/W
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1181BDGG-T | 制造商:ST-Ericsson 功能描述:USB Peripheral Controller 48-Pin TSSOP T/R |
| ISP1181BDGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181BPC | 制造商:ST-Ericsson 功能描述:Full-Speed Universal Serial Bus Peripheral Controller |
| ISP1181BS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| ISP1181DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
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