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參數(shù)資料
| 型號(hào)： | ISP1181BDGG,112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 20/70頁 |
| 文件大?。?/td> | 341K |
| 代理商： | ISP1181BDGG,112 |
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Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
27 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.3
Write/Read Mode Register
This command is used to access the ISP1181B Mode Register, which consists of
1 byte (bit allocation: see Table 18). In 16-bit bus mode the upper byte is ignored.
The Mode Register controls the DMA bus width, resume and suspend modes,
interrupt activity and SoftConnect operation. It can be used to enable debug mode,
where all errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (Hex): B8/B9 — write/read Mode Register
Transaction — write/read 1 byte
[1]
Unchanged by a bus reset.
Table 17:
Address Register: bit description
Bit
Symbol
Description
7
DEVEN
A logic 1 enables the device.
6 to 0
DEVADR[6:0]
This eld species the USB device address.
Table 18:
Mode Register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DMAWD
reserved
GOSUSP
reserved
INTENA
DBGMOD
reserved
SOFTCT
Reset
000
Access
R/W
Table 19:
Mode Register: bit description
Bit
Symbol
Description
7
DMAWD
A logic 1 selects 16-bit DMA bus width (bus conguration modes
0 and 2). A logic 0 selects 8-bit DMA bus width.
Bus reset value: unchanged.
6
-
reserved
5
GOSUSP
Writing a logic 1 followed by a logic 0 will activate ‘suspend’
mode.
4
-
reserved
3
INTENA
A logic 1 enables all interrupts. Bus reset value: unchanged.
2
DBGMOD
A logic 1 enables debug mode. where all NAKs and errors will
generate an interrupt. A logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints).
Bus reset value: unchanged.
1
-
reserved
0
SOFTCT
A logic 1 enables SoftConnect (see Section 7.4). This bit is
ignored if EXTPUL = 1 in the Hardware Conguration Register
(see Table 20). Bus reset value: unchanged.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1181BDGG-T | 制造商:ST-Ericsson 功能描述:USB Peripheral Controller 48-Pin TSSOP T/R |
| ISP1181BDGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181BPC | 制造商:ST-Ericsson 功能描述:Full-Speed Universal Serial Bus Peripheral Controller |
| ISP1181BS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| ISP1181DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
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