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參數(shù)資料
| 型號： | ISP1181BDGG,112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 22/70頁 |
| 文件大?。?/td> | 341K |
| 代理商： | ISP1181BDGG,112 |
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Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
29 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.5
Write/Read Interrupt Enable Register
This command is used to individually enable/disable interrupts from all endpoints, as
well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend,
resume, reset). A bus reset will not change any of the programmed bit values.
The command accesses the Interrupt Enable Register, which consists of 4 bytes. The
bit allocation is given in Table 22.
Code (Hex): C2/C3 — write/read Interrupt Enable Register
Transaction — write/read 4 bytes
6
DRQPOL
Selects DREQ signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
5
DAKPOL
Selects DACK signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
4
EOTPOL
Selects EOT signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
3
WKUPCS
A logic 1 enables remote wake-up via a LOW level on input CS
(For wake-up on CS to work, VBUS must be present). Bus reset
value: unchanged.
2
PWROFF
A logic 1 enables powering-off during ‘suspend’ state. Output
SUSPEND is congured as a power switch control signal for
external devices (HIGH during ‘suspend’). This value should
always be initialized to logic 1. Bus reset value: unchanged.
1
INTLVL
Selects the interrupt signalling mode on output INT (0 = level,
1 = pulsed). In pulsed mode an interrupt produces an 166 ns
pulse. See Section 13 for details. Bus reset value: unchanged.
0
INTPOL
Selects INT signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
Table 21:
Hardware Conguration Register: bit description…continued
Bit
Symbol
Description
Table 22:
Interrupt Enable Register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
IEP14
IEP13
IEP12
IEP11
IEP10
IEP9
IEP8
IEP7
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
IEP6
IEP5
IEP4
IEP3
IEP2
IEP1
IEP0IN
IEP0OUT
Reset
00000000
Access
R/W
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1181BDGG-T | 制造商:ST-Ericsson 功能描述:USB Peripheral Controller 48-Pin TSSOP T/R |
| ISP1181BDGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181BPC | 制造商:ST-Ericsson 功能描述:Full-Speed Universal Serial Bus Peripheral Controller |
| ISP1181BS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| ISP1181DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
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