參數(shù)資料
型號(hào)： ISP1563BM,557
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁(yè)數(shù)： 20/102頁(yè)
文件大?。?/td> 466K
代理商： ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
24 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
8.2.1.16
MIN_GNT and MAX_LAT registers
The Minimum Grant (MIN_GNT) and Maximum Latency (MAX_LAT) registers are used to
specify the desired settings of the device for latency timer values. For both registers, the
value species a period of time in units of 250 ns. Logic 0 indicates that the device has no
major requirements for setting latency timers.
The MIN_GNT register bit description is given in Table 23.
[1]
X is 01h for OHCI1 and OHCI2; X is 02h for EHCI.
The MAX_LAT register bit description is given in Table 24.
[1]
X is 2Ah for OHCI1 and OHCI2; X is 10h for EHCI.
8.2.1.17
TRDY _TIMEOUT - TRDY Timeout register
This is a read and write register at address 40h. The default and recommended value is
00h; TRDY time-out disabled. This value can, however, be modied. It is an
implementation-specic register, and not a standard PCI conguration register.
The TRDY timer is 13 bits: the lower 5 bits are xed as logic 0, and the upper 8 bits are
determined by the TRDY Timeout register value. The time-out is calculated by multiplying
the 13-bit timer with the PCICLK cycle time.
This register determines the maximum TRDY delay, without asserting the UE
(Unrecoverable Error) bit. If TRDY is longer than the delay determined by this register
value, then the UE bit will be set.
8.2.1.18
RETRY__TIMEOUT - Retry Timeout register
The default value of this read and write register is 80h, and is located at address 41h. This
value can, however, be modied. Programming this register as 00h means that retry
time-out is disabled. This is an implementation-specic register, and not a standard PCI
conguration register.
The time-out is determined by multiplying the register value with the PCICLK cycle time.
This register determines the maximum number of PCI retires before the UE bit is set. If the
number of retries is longer than the delay determined by this register value, then the UE
bit will be set.
Table 23.
MIN_GNT - Minimum Grant register (address 3Eh) bit description
Legend: * reset value
Bit
Symbol
Access
Value
Description
7 to 0
MIN_GNT[7:0] R
X*[1]
MIN_GNT: It is used to specify how long a burst period the device needs,
assuming a clock rate of 33 MHz.
Table 24.
MAX_LAT - Maximum Latency register (address 3Fh) bit description
Legend: * reset value
Bit
Symbol
Access
Value
Description
7 to 0
MAX_LAT[7:0]
R
MAX_LAT: It is used to specify how often the device needs to gain access
to the PCI bus.
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