參數(shù)資料
型號(hào)： ISP1563BM,557
廠商： ST-ERICSSON
元件分類(lèi)： 總線(xiàn)控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁(yè)數(shù)： 22/102頁(yè)
文件大小： 466K
代理商： ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
26 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
8.2.2.3
PORTWAKECAP register
Port Wake Capability (PORTWAKECAP) is a 2-byte register used to establish a policy
about which ports are for wake events; see Table 30. Bit positions 15 to 1 in the mask
correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit
position indicates that a device connected below the port can be enabled as a wake-up
device and the port may be enabled for disconnect or connect, or overcurrent events as
wake-up events. This is an information only mask register. The bits in this register do not
affect the actual operation of the EHCI Host Controller. The system-specic policy can be
established by BIOS initializing this register to a system-specic value. The system
software uses the information in this register when enabling devices and ports for remote
wake-up.
8.2.3 Power management registers
8.2.3.1
CAP_ID register
The Capability Identier (CAP_ID) register when read by the system software as 01h
indicates that the data structure currently being pointed to is the PCI power management
data structure. Each function of a PCI device may have only one item in its capability list
with CAP_ID set to 01h. The bit description of the register is given in Table 32.
Table 29.
FLADJ value as a function of SOF cycle time
FLADJ value
SOF cycle time (480 MHz)
0 (00h)
59488
1 (01h)
59504
2 (02h)
59520
::
31 (1Fh)
59984
32 (20h)
60000
::
62 (3Eh)
60480
63 (3Fh)
60496
Table 30.
PORTWAKECAP - Port Wake Capability register (address 62h) bit description
Legend: * reset value
Bit
Symbol
Access
Value
Description
15 to 0 PORTWAKE
CAP[15:0]
R/W
001Fh*
Port Wake-Up Capability Mask: EHCI does not implement this feature.
Table 31.
Power Management registers
Offset
Register
Value read from address 34h + 0h
Capability Identier (CAP_ID)
Value read from address 34h + 1h
Next Item Pointer (NEXT_ITEM_PTR)
Value read from address 34h + 2h
Power Management Capabilities (PMC)
Value read from address 34h + 4h
Power Management Control/Status (PMCSR)
Value read from address 34h + 6h
Power Management Control/Status PCI-to-PCI Bridge
Support Extensions (PMCSR_BSE)
Value read from address 34h + 7h
Data
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