參數(shù)資料
型號(hào)： ISP1563BM,557
廠商： ST-ERICSSON
元件分類(lèi)： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁(yè)數(shù)： 57/102頁(yè)
文件大?。?/td> 466K
代理商： ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
58 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
11.1.22 HcRhPortStatus[4:1] register
The HcRhPortStatus[4:1] register is used to control and report port events on a per-port
basis. NumberofDownstreamPort represent the number of HcRhPortStatus registers that
are implemented in hardware. The lower word reects the port status. The upper word
reects status change bits. Some status bits are implemented with special write behavior.
If a transaction, token through handshake, is in progress when a write to change port
status occurs, the resulting port status change is postponed until the transaction
completes. Always write logic 0 to the reserved bits.
The bit allocation of the register is given in Table 85.
[1]
The reserved bits should always be written with the reset value.
1
OCI
Overcurrent Indicator: This bit reports overcurrent conditions when global reporting is implemented.
When set, an overcurrent condition exists. When cleared, all power operations are normal. If the
per-port overcurrent protection is implemented, this bit is always logic 0.
0
LPS
On read, Local Power Status: The root hub does not support the local power status feature.
Therefore, this bit is always read as logic 0.
On write, Clear Global Power: In global power mode (Power Switching Mode = 0), logic 1 is written to
this bit to turn off power to all ports (clear Port Power Status). In per-port power mode, it clears Port
Power Status only on ports whose Port Power Control Mask bit is not set. Writing logic 0 has no
effect.
Table 84.
HcRhStatus - Host Controller Root Hub Status register bit description …continued
Address: Content of the base address register + 50h
Bit
Symbol
Description
Table 85.
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit allocation
Address: Content of the base address register + 54h
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
PRSC
OCIC
PSSC
PESC
CSC
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
LSDA
PPS
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
PRS
POCI
PSS
PES
CCS
Reset
00000000
Access
R/W
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