參數(shù)資料
型號(hào)： ISP1563BM,557
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁(yè)數(shù)： 79/102頁(yè)
文件大?。?/td> 466K
代理商： ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
78 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
Port disabled
If the port has power control, software cannot change the state of the port until it sets port
power bits. Software must not attempt to change the state of the port until power is stable
on the port; maximum delay is 20 ms from the transition. For bit allocation, see Table 118.
[1]
The reserved bits should always be written with the reset value.
Table 118. PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit allocation
Address: Content of the base address register + 64h + (4
× Port Number 1) where Port Number is 1, 2, 3, 4
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
WKOC_E
WKDS
CNNT_E
WKCNNT_
E
PTC[3:0]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
PIC[1:0]
PO
PP
LS[1:0]
reserved[1]
PR
Reset
00100000
Access
R
R/W
R
Bit
7
6
5
4
3
2
1
0
Symbol
SUSP
FPR
OCC
OCA
PEDC
PED
ECSC
ECCS
Reset
00000000
Access
R/W
R
R/W
R
Table 119. PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description
Address: Content of the base address register + 64h + (4
× Port Number 1) where Port Number is 1, 2, 3, 4
Bit
Symbol
Description
31 to 23
reserved
-
22
WKOC_E
Wake on Overcurrent Enable: Default = 0. Setting this bit enables the port to be sensitive to
overcurrent conditions as wake-up events.[1]
21
WKDS
CNNT_E
Wake on Disconnect Enable: Default = 0. Setting this bit enables the port to be sensitive to
device disconnects as wake-up events.[1]
20
WKCNNT_E Wake on Connect Enable: Default = 0. Setting this bit enables the port to be sensitive to device
connects as wake-up events.[1]
19 to 16
PTC[3:0]
Port Test Control: Default = 0000b. When this eld is logic 0, the port is not operating in test
mode. A nonzero value indicates that it is operating in test mode and test mode is indicated by the
value. The encoding of the test mode bits are:
0000b — Test mode disabled
0001b — Test J_STATE
0010b — Test K_STATE
0011b — Test SE0_NAK
0100b — Test packet
0101b — Test FORCE_ENABLE
0110b to 1111b — reserved
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