參數(shù)資料
型號(hào)： ISP1563BM,557
廠(chǎng)商： ST-ERICSSON
元件分類(lèi)： 總線(xiàn)控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁(yè)數(shù)： 73/102頁(yè)
文件大小： 466K
代理商： ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
72 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
Table 106. USBSTS - USB Status register bit description
Address: Content of the base address register + 24h
Bit
Symbol
Description
31 to 16
reserved
-
15
ASS
Asynchronous Schedule Status: Default = 0. The bit reports the current real status of the
asynchronous schedule. If this bit is logic 0, the status of the asynchronous schedule is disabled.
If this bit is logic 1, the status of the asynchronous schedule is enabled. The Host Controller is
not required to immediately disable or enable the asynchronous schedule when software
changes ASE (bit 5 in the USBCMD register). When this bit and the ASE bit have the same
value, the asynchronous schedule is either enabled (1) or disabled (0).
14
PSSTAT
Periodic Schedule Status: Default = 0. This bit reports the current status of the periodic
schedule. If this bit is logic 0, the status of the periodic schedule is disabled. If this bit is logic 1,
the status of the periodic schedule is enabled. The Host Controller is not required to immediately
disable or enable the periodic schedule when software changes PSE (bit 4 in the USBCMD
register). When this bit and the PSE bit have the same value, the periodic schedule is either
enabled (1) or disabled (0).
13
RECL
Reclamation: Default = 0. This is a read-only status bit that is used to detect an empty
asynchronous schedule.
12
HCH
HC Halted: Default = 1. This bit is logic 0 when RS (bit 0 of the USBCMD register) is logic 1. The
Host Controller sets this bit to logic 1 after it has stopped executing because the RS bit is set to
logic 0, either by software or by the Host Controller hardware. For example, on an internal error.
11 to 6
reserved
-
5
IAA
Interrupt on Asynchronous Advance: Default = 0. The system software can force the Host
Controller to issue an interrupt the next time the Host Controller advances the asynchronous
schedule by writing logic 1 to IAAD (bit 6 in the USBCMD register). This status bit indicates the
assertion of that interrupt source.
4
HSE
Host System Error: The Host Controller sets this bit when a serious error occurs during a host
system access, involving the Host Controller module. In a PCI system, conditions that set this bit
include PCI parity error, PCI master abort and PCI target abort. When this error occurs, the Host
Controller clears RS (bit 0 in the USBCMD register) to prevent further execution of the scheduled
TDs.
3
FLR
Frame List Rollover: The Host Controller sets this bit to logic 1 when the frame list index rolls
over from its maximum value to zero. The exact value at which the rollover occurs depends on
the frame list size. For example, if the frame list size, as programmed in FLS[1:0] (bits 3 and 2 of
the USBCMD register), is 1024, the Frame Index register rolls over every time bit 13 of the
FRINDEX register toggles. Similarly, if the size is 512, the Host Controller sets this bit to logic 1
every time bit 12 of the FRINDEX register toggles.
2
PCD
Port Change Detect: The Host Controller sets this bit to logic 1 when any port (where PO (bit 13
of PORTSC) is cleared) changes to logic 1, or FPR (bit 6 of PORTSC) changes to logic 1 as a
result of a J-K transition detected on a suspended port. This bit is allowed to be maintained in the
auxiliary power well. Alternatively, it is also acceptable that on a D3-to-D0 transition of the EHCI
Host Controller device, this bit is loaded with the logical OR of all of the PORTSC change bits,
including force port resume, overcurrent change, enable or disable change, and connect status
change.
1
USBERRINT USB Error Interrupt: The Host Controller sets this bit when an error condition occurs because of
completing a USB transaction. For example, error counter underow. If the Transfer Descriptor
(TD) on which the error interrupt occurred also had its IOC bit set, both this bit and the USBINT
bit are set. For details, refer to
Enhanced Host Controller Interface Specication for Universal
Serial Bus Rev. 1.0.
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