參數(shù)資料
型號: ISP1760
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁數(shù): 22/105頁
文件大?。?/td> 449K
代理商: ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
22 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
The PLL block generates all the main internal clocks required for normal functionality of
various blocks: 30 MHz, 48 MHz and 60 MHz.
No external components are required for the PLL operation.
7.6 Power management
The ISP1760 implements a flexible power management scheme, allowing various power
saving stages.
The usual powering scheme implies programming EHCI registers and the internal
Hi-Speed USB (USB 2.0) hub in the same way it is done in the case of a PCI Hi-Speed
USB Host Controller with a Hi-Speed USB hub attached.
When the ISP1760 is in suspend mode, the main internal clocks will be stopped to ensure
minimum power consumption. An internal LazyClock of 100 kHz
±
40 % will continue
running. This allows initiating a resume on one of the following events:
External USB device connect or disconnect
Assertion of the CS_N signal because of any access to the ISP1760
Driving the SUSPEND/WAKEUP_N pin to a LOW level.
The SUSPEND/WAKEUP_N pin is a bidirectional pin. This pin should be connected to
one of the GPIO pins of a processor.
The awake state can be verified by reading the LOW level of this pin. If the level is HIGH,
it means that the ISP1760 is in the suspend state.
The SUSPEND/WAKEUP_N pin requires a pull-up because in the ISP1760 suspended
state the pin becomes three-state and can be pulled down, driving it externally by
switching the processor’s GPIO line to the output mode to generate the ISP1760 wake-up.
The SUSPEND/WAKEUP_N pin is a three-state output. It is also an input to the internal
wake-up logic.
When in suspend mode, the ISP1760 internal wake-up circuitry will sense the status of
the SUSPEND/WAKEUP_N pin:
If it remains pulled-up, no wake-up is generated because a HIGH is sensed by the
internal wake-up circuit.
If the pin is externally pulled LOW (for example, by the GPIO line or just as a test by
jumper), the input to the wake-up circuitry becomes LOW and the wake-up is
internally initiated.
The resume state has a clock-off count timer defined by bits 31 to 16 of the Power Down
Control register. The default value of this timer is 10 ms, meaning that the resume state
will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD
register is set to logic 1, the Host Controller will go into a permanent resume—the normal
functional state. If the RUN/STOP bit is not set during the time determined by the clock-off
count, the ISP1760 will switch back to suspend mode after the specified time. The
maximum delay that can be programmed in the clock-off count field is approximately
500 ms.
相關(guān)PDF資料
PDF描述
ISP1761 Hi-Speed Universal Serial Bus On-The-Go controller
ISP1761BE Hi-Speed Universal Serial Bus On-The-Go controller
ISP1761ET Hi-Speed Universal Serial Bus On-The-Go controller
ISP2100A Telecommunication IC
ISP2100BN4 Microprocessor
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