參數(shù)資料
型號(hào): ISP1760
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁數(shù): 43/105頁
文件大小: 449K
代理商: ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
43 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
8.3.6
Buffer Status register (R/W: 0334h)
Table 41
shows the bit allocation of the Buffer Status register.
[1]
The reserved bits should always be written with the reset value.
Table 40:
Bit
31 to 8
DMA Configuration register: bit description
Symbol
Description
DMA_COUNTER
[23:0]
write).
Remark:
Different number of bursts will be generated for the
same transfer length programmed in 16-bit and 32-bit modes
because DMA_COUNTER is in number of bytes.
-
reserved
BURST_LEN[1:0]
DMA Burst Length
:
00 —
Single DMA burst
01 —
4-cycle DMA burst
10 —
8-cycle DMA burst
11 —
16-cycle DMA burst.
ENABLE_DMA
Enable DMA
:
0 —
Terminate DMA
1 —
Enable DMA.
DMA_READ_
WRITE_SEL
write or read (to or from the ISP1760).
0 —
DMA write to the ISP1760 internal RAM is set
1 —
DMA read from the ISP1760 internal RAM.
DMA Counter
: The number of bytes to be transferred (read or
7 to 4
3 to 2
1
0
DMA Read/Write Select
: Indicates if the DMA operation is a
Table 41:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Buffer Status register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
reserved
[1]
ISO_BUF_
FILL
0
R/W
INT_BUF_
FILL
0
R/W
ATL_BUF_
FILL
0
R/W
Reset
Access
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
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