When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency o" />
參數(shù)資料
型號： ISPPAC-CLK5304S-01TN48C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 11/56頁
文件大小： 0K
描述： IC CLOCK PROGRAM BUFFER 48TQFP
標(biāo)準(zhǔn)包裝： 250
系列： ispClock™
類型： 時鐘發(fā)生器，扇出配送，零延遲緩沖器
PLL： 帶旁路
輸入： HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL
輸出： eHSTL，HSTL，LVCMOS，LVTTL，SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:4
差分 - 輸入:輸出： 是/無
頻率 - 最大： 267MHz
除法器/乘法器： 是/無
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
Lattice Semiconductor
ispClock5300S Family Data Sheet
19
When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency of each V divider (fk) may be cal-
culated as:
(1)
where
fk is the frequency of V divider k
fref is the input reference frequency
Vfbk is the setting of the V divider used to close the PLL feedback path
Vk is the output divider K
Note that because the feedback may be taken from any V divider, Vk and Vfbk may refer to the same divider.
Because the VCO has an operating frequency range spanning 160 MHz to 400 MHz, and the V dividers provide
division ratios from 1 to 32, the ispClock5300S can generate output signals ranging from 2.5 MHz to 267 MHz.
PLL_BYPASS Mode
The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without
using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the reference clock is
routed directly to the inputs of the V dividers. The output frequency for a given V divider (fK) will be determined by
(2)
When PLL_BYPASS mode is enabled, features such as lock detect and skew generation are unavailable and the
output clock is inverted when VK=1.
Internal/External Feedback Support
The PLL feedback path can be sourced internally or externally through an output pin. When the internal feedback
path is selected, one can use all output pins for clock distribution. The programmable skew feature for the feedback
path is available in both feedback modes.
Reference and External Feedback Inputs
The ispClock5300S provides congurable, internally-terminated inputs for both clock reference and feedback sig-
nals.
The reference clock inputs pins can be interfaced with either one differential input (REFP, REFN) or two single-
ended (REFA, REFB) inputs with the active clock selection control through REFSEL pin. The following diagram
shows the possible reference clock congurations. Note: When the reference clock inputs are congured as differ-
ential input, the REFSEL pin should be grounded.
Table 2. REFSEL Operation for ispClock5300S Programmed as Single-Ended Clock Inputs
Supported input logic reference standards:
LVTTL (3.3V)
LVCMOS (1.8V, 2.5V, 3.3V)
SSTL2
SSTL3
HSTL
REFSEL
Selected
Input
0
REFA
1
REFB
=
fk
fref
Vfbk
Vk
=
fk
fREF
VK
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5304S-01TN48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5304S-01TN48I 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5304S-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5304S-01TN64C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5304S-01TN64I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
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