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參數(shù)資料
| 型號： | ISPPAC-CLK5304S-01TN48C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 26/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK PROGRAM BUFFER 48TQFP |
| 標準包裝： | 250 |
| 系列： | ispClock™ |
| 類型： | 時鐘發(fā)生器，扇出配送，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
32
(fVCO = 400MHz) to 780ps (fVCO = 160MHz), which is twice as long as those provided in ne skew mode. When
coarse skew mode is selected, an additional divide-by-2 stage is effectively inserted between the VCO and the V-
divider bank, as shown in Figure 26. When assigning divider settings in coarse skew mode, one must account for
this additional divide-by-two so that the VCO still operates within its specied range (160-400MHz).
Figure 26. Additional Factor-of-2 Division in Coarse Mode
When one moves from ne skew mode to coarse skew mode with a given divider conguration, the VCO frequency
will attempt to double to compensate for the additional divide-by-2 stage. Because the fVCO range is not increased,
however, one must modify the feedback path V-divider settings to bring fVCO back into its specied operating range
(160MHz to 400MHz). This can be accomplished by dividing all V-divider settings by two. All output frequencies will
remain unchanged from what they were in ne mode.
Output Skew Matching and Accuracy
Understanding the various factors which relate to output skew is essential for realizing optimal skew performance in
the ispClock5300S family of devices.
In the case where two outputs are identically congured, and driving identical loads, the maximum skew is dened
by tSKEW, which is specied as a maximum of 100ps. In Figure 27 the Bank1A and BANK2A outputs show the skew
error between two matched outputs.
Figure 27. Skew Matching Error Sources
One can also program a user-dened skew between two outputs using the skew control units. Because the pro-
grammable skew is derived from the VCO frequency, as described in the previous section, the absolute skew is
very accurate. The typical error for any non-zero skew setting is given by the tSKERR specication. For example, if
one is in ne skew mode with a VCO frequency of 250MHz, and selects a skew of 4TU, the realized skew will be
1ns, which will typically be accurate to within +/-30 ps. An example of error vs. skew setting can be found in the
chart ‘Typical Skew Error vs. Setting’ in the typical performance characteristics section. Note that this parameter
adds to output-to-output skew error only if the two outputs have different skew settings. The Bank1A and Bank3A
VCO
÷2
V-dividers
Fine
Mode
Fout
Coarse
Mode
+/- t
SKEW
1ns +/- (t
SKEW) +/- (tSKERR)
BANK1A
(skew setting = 0)
BANK2A
(skew setting=0)
BANK3A
(skew setting = 1ns)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5304S-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5304S-01TN48I | 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5304S-01TN64C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5304S-01TN64I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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