參數(shù)資料
型號: ISPPAC-CLK5304S-01TN48C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 37/56頁
文件大小: 0K
描述: IC CLOCK PROGRAM BUFFER 48TQFP
標(biāo)準(zhǔn)包裝: 250
系列: ispClock™
類型: 時鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 是/無
頻率 - 最大: 267MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
Lattice Semiconductor
ispClock5300S Family Data Sheet
42
Pin Descriptions – ispClock5304S, 5308S, 5312S
Pin Name
Description
Pin Type
Pin Number
ispClock5304S
48 TQFP
ispClock5308S
48 TQFP
ispClock5312S
48 TQFP
VCCO_0
Output Driver ‘0’ VCC
Power
5
1
VCCO_1
Output Driver ‘1’ VCC
Power
32
9
5
VCCO_2
Output Driver ‘2’ VCC
Power
28
9
VCCO_3
Output Driver ‘3’ VCC
Power
32
28
VCCO_4
Output Driver ‘4’ VCC
Power
32
VCCO_5
Output Driver ‘5’ VCC
Power
36
GNDO_0
Output Driver ‘0’ Ground
GND
7
3
GNDO_1
Output Driver ‘1’ Ground
GND
30
11
7
GNDO_2
Output Driver ‘2’ Ground
GND
26
11
GNDO_3
Output Driver ‘3’ Ground
GND
30
26
GNDO_4
Output Driver ‘4’ Ground
GND
30
GNDO_5
Output Driver ‘5’ Ground
GND
34
BANK_0A
Clock Output driver 0, ‘A’ output
Output
6
2
BANK_0B
Clock Output driver 0, ‘B’ output
Output
8
4
BANK_1A
Clock Output driver 1, ‘A’ output
Output
31
10
6
BANK_1B
Clock Output driver 1, ‘B’ output
Output
29
12
8
BANK_2A
Clock Output driver 2, ‘A’ output
Output
27
10
BANK_2B
Clock Output driver 2, ‘B’ output
Output
25
12
BANK_3A
Clock Output driver 3, ‘A’ output
Output
31
27
BANK_3B
Clock Output driver 3, ‘B’ output
Output
29
25
BANK_4A
Clock Output driver 4, ‘A’ output
Output
31
BANK_4B
Clock Output driver 4, ‘B’ output
Output
29
BANK_5A
Clock Output driver 5, ‘A’ output
Output
35
BANK_5B
Clock Output driver 5, ‘B’ output
Output
33
VCCA
Analog VCC for PLL circuitry
Power
46
GNDA
Analog Ground for PLL circuitry
GND
47
VCCD
Digital Core VCC
Power
21, 22
GNDD
Digital GND
GND
23, 24, 48
REFA_REFP
Clock Reference A/Positive Differential
input
3
Input
14
REFB_REFN Clock Reference B/Negative Differential
input
3
Input
15
REFSEL
Clock Reference Select input (LVCMOS)
Input
1
19
VTT_REFA
Termination voltage for reference input A
Power
13
FBK
Feedback Input
3
Input
17
VTT_FBK
Termination voltage for feedback input
Power
18
VTT_REFB
Termination input for reference input B
Power
16
VCCJ
JTAG interface VCC
Power
41
TDO
JTAG TDO Output line
Output
37
TDI
JTAG TDI Input line
Input
2
40
TCK
JTAG Clock Input
Input
39
TMS
JTAG Mode Select
Input
2
38
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ISPPACCLK5304S-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5304S-01TN64C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
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