參數(shù)資料
型號(hào): ISPPAC-CLK5304S-01TN48C
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 23/56頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK PROGRAM BUFFER 48TQFP
標(biāo)準(zhǔn)包裝: 250
系列: ispClock™
類型: 時(shí)鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 是/無(wú)
頻率 - 最大: 267MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
Lattice Semiconductor
ispClock5300S Family Data Sheet
3
Figure 2. ispClock5308S Functional Block Diagram
Figure 3. ispClock5312S Functional Block Diagram
+
VCO
LOOP
FILTER
PHASE
DETECT
LOCK
DETECT
1
0
OEX
S
A
P
Y
B
_
L
P
K
C
O
L
JTAG INTERFACE
OEY
SKEW
CONTROL
OUTPUT
DRIVERS
SKEW
CONTROL
OUTPUT
DRIVERS
OUTPUT
DIVIDERS
OUTPUT ROUTING
MATRIX
RESET
V1
V2
V0
BANK_0A
BANK_0B
BANK_1A
BANK_1B
BANK_2A
BANK_2B
BANK_3A
BANK_3B
OUTPUT ENABLE
CONTROLS
5-bit
0
1
REFA_REFP
REFSEL
VTT_REFB
REFB_REFN
VTT_REFA
VTT_FBK
FBK
TDO
TCK
TMS
TDI
VCO
LOOP
FILTER
PHASE
DETECT
LOCK
DETECT
1
0
OEX
S
A
P
Y
B
_
L
P
K
C
O
L
JTAG INTERFACE
OEY
SKEW
CONTROL
OUTPUT
DRIVERS
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_5A
BANK_5B
OUTPUT
DIVIDERS
OUTPUT ROUTING
MATRIX
RESET
V1
V2
V0
BANK_0A
BANK_0B
BANK_1A
BANK_1B
BANK_2A
BANK_2B
BANK_3A
BANK_3B
BANK_4A
BANK_4B
OUTPUT ENABLE
CONTROLS
5-bit
0
1
REFA_REFP
REFSEL
VTT_REFB
REFB_REFN
VTT_REFA
+
VTT_FBK
FBK
TDO
TCK
TMS
TDI
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ISPPACCLK5304S-01TN48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
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ISPPACCLK5304S-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5304S-01TN64C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5304S-01TN64I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended