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參數(shù)資料
| 型號： | ISPPAC-CLK5304S-01TN48C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 36/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK PROGRAM BUFFER 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | ispClock™ |
| 類型： | 時鐘發(fā)生器，扇出配送，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
41
In addition to the four instructions described above, there are 20 unique instructions specied by Lattice for the
ispClock5300S. These instructions are primarily used to interface to the various user registers and the E
2CMOS
non-volatile memory. Additional instructions are used to control or monitor other features of the device, including
boundary scan operations. A brief description of each unique instruction is provided in detail below, and the bit
codes are found in Table 4.
PROGRAM_ENABLE – This instruction enables the ispClock5300S programming mode.
PROGRAM_DISABLE – This instruction disables the ispClock5300S programming mode.
BULK_ERASE – This instruction will erase all E
2CMOS bits in the device, including the UES data and electronic
security fuse (ESF). A bulk erase instruction must be issued before reprogramming a device. The device must
already be in programming mode for this instruction to execute.
ADDRESS_SHIFT – This instruction shifts address data into the address register (10 bits) in preparation for either
a PROGRAM or VERIFY instruction.
DATA_SHIFT – This instruction shifts data into or out of the data register (43 bits for ispClock5312, 5308 and 5304;
61 bits for ispClock5320 and 5316), and is used with both the PROGRAM and VERIFY instructions.
PROGRAM – This instruction programs the contents of the data register to the E
2CMOS memory column pointed
to by the address register. The device must already be in programming mode for this instruction to execute.
PROG_INCR – This instruction rst programs the contents of the data register into E
2CMOS memory column
pointed to by the address register and then auto-increments the value of the address register. The device must
already be in programming mode for this instruction to execute.
PROGRAM_SECURITY – This instruction programs the electronic security fuse (ESF). This prevents data other
than the ID code and UES strings from being read from the device. The electronic security fuse may only be reset
by issuing a BULK_ERASE command. The device must already be in programming mode for this instruction to exe-
cute.
VERIFY – This instruction loads data from the E
2CMOS array into the column register. The data may then be
shifted out. The device must already be in programming mode for this instruction to execute.
VERIFY_INCR – This instruction copies the E
2CMOS column pointed to by the address register into the data col-
umn register and then auto-increments the value of the address register. The device must already be in program-
ming mode for this instruction to execute.
DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispClock5300S for a read cycle.
PROGRAM_USERCODE – This instruction writes the contents of the UES register (32 bits) into E
2CMOS memory.
The device must already be in programming mode for this instruction to execute.
USERCODE – This instruction both reads the UES string (32 bits) from E
2CMOS memory into the UES register
and addresses the UES register so that this data may be shifted in and out.
HIGHZ – This instruction forces all outputs into a High-Z state.
CLAMP – This instruction drives I/O pins with the contents of the boundary scan register.
INTEST – This instruction performs in-circuit functional testing of the device.
ERASE_DONE – This instruction erases the ‘DONE’ bit only. This instruction is used to disable normal operation of
the device while in programming mode until a valid conguration pattern has been programmed.
PROGRAM_DONE – This instruction programs the ‘DONE’ bit only. This instruction is used to enable normal
device operation after programming is complete.
NOOP – This instruction behaves similarly to the CLAMP instruction.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5304S-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5304S-01TN48I | 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5304S-01TN64C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5304S-01TN64I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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