參數(shù)資料
型號(hào): ISPPAC-CLK5308S-01T48C
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 3/56頁(yè)
文件大?。?/td> 0K
描述: IC BUFFER FANOUT ISP UNIV 48TQFP
標(biāo)準(zhǔn)包裝: 250
系列: ispClock™
類型: 時(shí)鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:8
差分 - 輸入:輸出: 是/無(wú)
頻率 - 最大: 267MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
Lattice Semiconductor
ispClock5300S Family Data Sheet
11
Performance Characteristics – PLL
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fREF, fFBK
Reference and feedback input
frequency range
8
267
MHz
tCLOCKHI,
tCLOCKLO
Reference and feedback input
clock HIGH and LOW times
1.25
ns
tRINP,
tFINP
Reference and feedback input
rise and fall times
Measured between 20% and 80%
levels
5ns
fPFD
Phase detector input frequency
range
8
267
MHz
fVCO
VCO operating frequency
160
400
MHz
VDIV
Output divider range (Power of
2)
132
fOUT
Output frequency range
1
Fine Skew Mode
5
267
MHz
Coarse Skew Mode
2.5
200
MHz
tJIT (cc)
Output adjacent-cycle jitter
5
(1000 cycle sample)
fPFD ≥ 100MHz
70
ps (p-p)
tJIT (per)
Output period jitter
5
(10000 cycle sample)
fPFD ≥ 100MHz
9
ps (RMS)
tJIT(φ)
Reference clock to output jitter
5
(2000 cycle sample)
fPFD ≥ 100MHz
50
ps (RMS)
Static phase offset
4
PFD input frequency ≥100MHz
3
-40
100
ps
DYN
Dynamic phase offset
100MHz, Spread Spectrum
Modulation index = 0.5%
28
ps
DCERR
Output duty cycle error
Output type LVCMOS 3.3V
2
fOUT >100 MHz
47
53
%
tPDBYPASS
Reference clock to output
propagation delay
V=1
6.5
ns
tPD_FOB
Reference to output propagation
delay in Non-Zero Delay Buffer
Mode
V=1
2.5
3.5
5
ns
tDELAY
Reference to output delay with
internal feedback mode
3
V=1
500
ps
tLOCK
PLL lock time
From Power-up event
150
s
From RESET event
15
s
tRELOCK
PLL relock time
To same reference frequency
15
s
To different frequency
150
s
PSR
Power supply rejection, period
jitter vs. power supply noise
fIN = fOUT = 100MHz
VCCA = VCCD = VCCO modulated with
100kHz sinusoidal stimulus
0.05
1. In PLL Bypass mode (PLL_BYPASS = HIGH), output will support frequencies down to 0Hz (divider chain is a fully static design).
2. See Figures 6 and 7 for output loads.
3. Input and outputs LVCMOS mode
4. Inserted feedback loop delay < 7ns
5. Measured with fOUT = 100MHz, fVCO = 400MHz, input and output interface set to LVCMOS.
ps(RMS)
mV(p-p)
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ISPPACCLK5308S-01T48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
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