- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9101 > ISPPAC-CLK5308S-01T48C (Lattice Semiconductor Corporation)IC BUFFER FANOUT ISP UNIV 48TQFP PDF資料下載
參數(shù)資料
| 型號： | ISPPAC-CLK5308S-01T48C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 41/56頁 |
| 文件大小： | 0K |
| 描述： | IC BUFFER FANOUT ISP UNIV 48TQFP |
| 標準包裝： | 250 |
| 系列： | ispClock™ |
| 類型： | 時鐘發(fā)生器，扇出配送，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
Lattice Semiconductor
ispClock5300S Family Data Sheet
46
Detailed Pin Descriptions
VCCO_[0..9], GNDO_[0..9] – These pins provide power and ground for each of the output banks. In the case when
an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should be tied to
ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When
a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1F as close to its
VCCO and GNDO pins as is practical.
BANK_[0..9]A, BANK_[0..9]B – These pins provide clock output signals. The choice of output driver type (CMOS,
SSTL, etc.) may be selected on a bank-by-bank basis. The output impedance and slew rate may be selected on an
output-by-output basis.
VCCA, GNDA – These pins provide analog supply and ground for the ispClock5300S family’s internal analog cir-
cuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. To improve noise immu-
nity, it is suggested that the supply to the VCCA pin be isolated from other circuitry with a ferrite bead.
VCCD, GNDD – These pins provide digital supply and ground for the ispClock5300S family’s internal digital cir-
cuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. To improve noise immu-
nity it is suggested that the supply to the VCCD pins be isolated with ferrite beads.
VCCJ – This pin provides power and a reference voltage for use by the JTAG interface circuitry. It may be set to
allow the ispClock5300S family devices to function in JTAG chains operating at voltages differing from VCCD.
REFA_REFP, REFB_REFN – These input pins provide the inputs for clock signals, and can accommodate either
single ended or differential signal protocols.
REFSEL – This input pin is used to select which clock input pair (REFA or REB) is selected for use as the reference
input. When REFSEL=0, REFA is used, and when REFSEL=1, REFB is used.
VTT_REFA, VTT_REFB – These pins are used to provide a termination voltage for the reference inputs when they
are congured for SSTL or HSTL logic, and should be connected to a suitable voltage supply in those cases.
FBK – This input pin provides feedback sense of the output clock signal, and can accommodate any of the single-
ended logic types.
VTT_FBK – This pin is used to provide a termination voltage for the feedback input when it is congured for SSTL
or HSTL logic, and should be connected to a suitable voltage supply in those cases.
TDO, TDI, TCK, TMS – These pins comprise the ispClock5300S device’s JTAG interface. The signal levels for these
pins are determined by the selection of the VCCJ voltage.
LOCK – This output pin indicates that the device’s PLL is in a locked condition when it goes HIGH.
OEX, OEY – These pins are used to enable the outputs or put them into a high-impedance condition. Each output
may be set so that it is always on, always off, enabled by OEX or enabled by OEY.
PLL_BYPASS – When this pin is pulled LOW, the V-dividers are driven from the output of the device’s VCO, and
the device behaves as a phase-locked loop. When this pin is pulled HIGH, the V-dividers are driven directly from a
selected reference input, and the PLL functions are effectively bypassed.
RESET – When this pin is pulled LOW, all on-board counters are reset, and lock is lost. If the RESET pin is not
driven by an external logic it should be pulled up to VCCD through a 10kΩ resistor.
NC – These pins have no internal connection. It is recommended that they be left unconnected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-274-MW-S | CONVERTER MOD DC/DC 48V 100W |
| VI-24H-IV | CONVERTER MOD DC/DC 52V 150W |
| ADF4156BRUZ-RL | IC PLL FRAC-N FREQ SYNTH 16TSSOP |
| SY100S838ZG TR | IC CLOCK GEN 3.3V/5V 20-SOIC |
| VI-24K-IV | CONVERTER MOD DC/DC 40V 150W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5308S-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5308S-01T48I | 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5308S-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5308S-01T64C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5308S-01T64I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
發(fā)布緊急采購，3分鐘左右您將得到回復。