參數(shù)資料
型號(hào): IXF1010
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552
封裝: 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552
文件頁(yè)數(shù): 104/116頁(yè)
文件大小: 1392K
代理商: IXF1010
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IXF1010 — 10-Port 100/1000 Mbps Ethernet MAC
88
Preliminary Datasheet
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
6.5.4
Global Status and Configuration Register Overview
Table 61 through Table 70 on page 93 provide an overview for the Global Control and Status
Registers.
Tagged
Number of OK frames with VLAN tag.
(Type field = 0x8100).
Port_Index +
0x55
RR
0x00000000
CRCError
Number of frames transmitted with a
legal size, but with the wrong CRC field
(also called FCS field)
Port_Index +
0x56
RR
0x00000000
TxPauseFrames
Number of pause MAC frames
transmitted
Port_Index +
0x57
RR
0x00000000
FlowControlCollisionsSend
Collisions generated on purpose on
incoming frames, to avoid reception of
traffic, while the port is in half-duplex
and has flow control enabled, and do
not have sufficient memory to receive
more frames.
Note: Due to the internal counting
technique, a last frame might have to
be transmitted after last flow control
collision send to get the correct
statistic.
Note: N/A - half-duplex only
Port_Index +
0x58
RR
0x00000000
Table 60. STAT-TX Registers (Addr: Port_Index + 0x40 - Port_Index + 0x58) (Continued)
Name
Description
Address
Type1
Default
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
Table 61. Port Enable Register
Name
Description
Address
Type1
Default
Port Enable
Register
A control register for each port in IXF1010.
Port ID = bit position in the register. To make a
port active, the bit must be set High (for
example, port 4 active implies register value =
0001.0000). Setting the bit to 0 de-asserts the
reset. The default state for this register is for
all 10 ports to be active.
0x500
R/W
0x000003FF
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
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