參數(shù)資料
型號： IXF1010
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552
封裝： 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552
文件頁數(shù)： 30/116頁
文件大?。?/td> 1392K
代理商： IXF1010
IXF1010 — 10-Port 100/1000 Mbps Ethernet MAC
20
Preliminary Datasheet
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
3.1.2.2
Automatic CRC Generation
The Automatic CRC Generation is used in conjunction with the padding feature to generate and
append a correct CRC to any incoming frame from the SPI4-2. This feature is enabled by setting bit
6 of the DiverseConfigWrite Register = 1 (Address Port_Index + 0x18h).
Note:
When padding of undersized frames on transmit is enabled, the automatic CRC generation must be
enabled for proper operation of the IXF1010.
3.1.2.3
Filtering of Receive Packets
This feature allows the MAC to filter receive packets under various conditions and drop the
packets via an interaction with the Receive FIFO control.
3.1.2.3.1
Filter on Unicast Packet Match
This feature is enabled when bit 0 of the PacketFilterControl Register = 1. Any frame received in
this mode that does not match the StationAddress is marked by the MAC to be dropped. The frame
is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable Register = 1.
Otherwise, all unicast frames are sent to the SPI4-2 interface.
3.1.2.3.2
Filter on Multicast Packet Match
This feature is enabled when bit 1 of the PacketFilterControl Register = 1. Any frame received in
this mode that does not match the PortMulticastAddress is marked by the MAC to be dropped. The
frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable register = 1.
Otherwise, all multicast frames are sent to the SPI4-2 interface.
3.1.2.3.3
Filter Broadcast Packets
This feature is enabled when bit 2 of the PacketFilterControl Register = 1. Any broadcast frame
received in this mode is marked by the MAC to be dropped. The frame is dropped if the appropriate
bit in the RX FIFO Errored Frame Drop Enable Register = 1. Otherwise, all broadcast frames are
sent to the SPI4-2 interface.
3.1.2.3.4
Filter VLAN Packets
This feature is enabled when bit 3 of the PacketFilterControl Register = 1. VLAN frames received
in this mode are marked by the MAC to be dropped. The frame is dropped if the appropriate bit in
the RX FIFO Errored Frame Drop Enable Register = 1. Otherwise, all VLAN frames are sent to the
SPI4-2.
3.1.2.3.5
Filter PAUSE Packets
This feature is enabled when bit 4 of the PacketFilterControl Register = 0. PAUSE frames received
in this mode are marked by the MAC to be dropped. The frame is dropped if the appropriate bit in
the RX FIFO Errored Frame Drop Enable Register = 1. Otherwise, all PAUSE frames are sent to
the SPI4-2.
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