參數(shù)資料
型號： IXF1010
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552
封裝： 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552
文件頁數(shù)： 7/116頁
文件大?。?/td> 1392K
代理商： IXF1010
IXF1010 — 10-Port 100/1000 Mbps Ethernet MAC
104
Preliminary Datasheet
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
Table 78. MAC Transfer Threshold Ports 0 to 9 (Addr: 0x614 - 0x61D)
Name2
Description3
Address
Type1
Default
MAC Transfer
Threshold Port 0
Sets the value at which the FIFO begins to
transfer data to the MAC. The bottom 3 bits of
this register are ignored, and the threshold is
set in increments of 8-byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
0x614
R/W
0x00000040
MAC Transfer
Threshold Port 1
Sets the value at which the FIFO begins to
transfer data to the MAC. The bottom 3 bits of
this register are ignored, and the threshold is
set in increments of 8-byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
0x615
R/W
0x00000040
MAC Transfer
Threshold Port 2
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
0x616
R/W
0x00000040
MAC Transfer
Threshold Port 3
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
0x617
R/W
0x00000040
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
2. For all MAC Transfer Threshold Registers, the following bit definitions apply to all ports (0:9):
Bits 31:13 - Reserved and RO.
Bits 12:0 - Described above.
3. For proper operation of the IXF1010, the MAC transfer threshold must be set to greater than the MaxBurst1
on the SPI4-2.
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