參數(shù)資料
型號(hào)： IXF1010
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552
封裝： 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552
文件頁數(shù)： 21/116頁
文件大小： 1392K
代理商： IXF1010
IXF1010 — 10-Port 100/1000 Mbps Ethernet MAC
12
Preliminary Datasheet
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
2.0
Pin Assignments and Signal Descriptions
Figure 4 and Table 1 through Table 3 provide the signal pins used by the IXF1010
2.1
Signal Name Conventions
Signal names may contain either a port designation (PHY interface) or a serial designation (System
Interface). Signal naming conventions are as follows:
Port Designation. Individual signals that apply to a particular port are designated by the Signal
Mnemonic, immediately followed by an underscore and the Port Designation. For example,
RGMII Transmit Control signals would be identified as TX_CTL_0, TX_CTL_1, TX_CTL_2, etc.
Serial Designation. A set of signals that are not tied to any specific port are designated by the
Signal Mnemonic, followed by an bracketed serial designation. For example, SPI4-2 Transmit Data
Bus signals would be identified as TDAT[15:0].
Port Bus Designation: A set of bus signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by a bracketed bus designation, followed by an
underscore and the port designation. For example, RGMII transmit data bus signals would be
identified as TD[3:0]_0, TD[3:0]_1, TD[3:0]_2, etc.
Figure 4. IXF1010 Pinout Diagram
IXF1010
TDAT[15:0]+/-
TDO
MDIO
RSCLK
RCTL+/-
RDCLK+/-
RSTAT[1:0]
RDAT[15:0]+/-
TSCLK
TCTL+/-
TDCLK+/-
TSTAT[1:0]
uPx_Add[10:0]
uPx_Data[31:0]
TxPauseFr
TxPauseAdd[3:0]
MDC
TCLK
TDI
TMS
uPx_Wr
uPx_Rd
uPx_Cs
uPx_Rdy
JTAG
Interface
MDIO
Interface
CPU
Interface
TXC_9:0
RX_CTL_9:0
RXC_9:0
TX_CTL_9:0
TD[3:0]_9
RD[3:0]_9
RGMII
Interface
SPI4-2
Phase 2
Interface
TD[3:0]_8
TD[3:0]_7
TD[3:0]_6
TD[3:0]_5
TD[3:0]_4
TD[3:0]_3
TD[3:0]_2
TD[3:0]_1
TD[3:0]_0
RD[3:0]_1
RD[3:0]_2
RD[3:0]_3
RD[3:0]_4
RD[3:0]_5
RD[3:0]_6
RD[3:0]_7
RD[3:0]_8
RD[3:0]_0
Pause Control
Interface
LED
Interface
LED_CLK
LED_LATCH
LED_DATA
CLK125
System
Interface
CLK50
Sys_Res
TRST
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