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參數(shù)資料
| 型號(hào)： | KIT33989DWEVB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 13/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL 33989DW HS SBC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，CAN 控制器 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | MC33989 |
| 主要屬性： | CAN 2.0 系統(tǒng)基礎(chǔ)芯片（SBC），SPI 接口，2 低壓降穩(wěn)壓器 |
| 次要屬性： | 故障檢測，睡眠和待機(jī)模式 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | MC33989DWR2CT-ND - IC SYSTEM BASE W/CAN 28-SOIC MC33989DWR2TR-ND - IC SYSTEM BASE W/CAN 28-SOIC MC33989DW-ND - IC SYSTEM BASE W/CAN 28-SOIC |
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Analog Integrated Circuit Device Data
20
Freescale Semiconductor
33989
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
DEVICE SUPPLY
The device is supplied from the battery line through the VSUP pin. An external diode is required to protect against negative
transients and reverse battery. It can operate from 4.5 V and under the jump start condition at 27 Vdc. This pin sustains standard
automotive voltage conditions such as load dump at 40 V. When VSUP falls below 3.0 V typical the 33989 detects it and stores
the information into the SPI register in a bit called BATFAIL. This detection is available in all operation modes.
The device incorporates a battery early warning function, providing a maskable interrupt when the VSUP voltage is below 6.0
V typical. A hysteresis is included. Operation is only in Normal and Standby modes. VSUP low is reported in the Input/Output
Register (IOR).
VDD1 VOLTAGE REGULATOR
The VDD1 Regulator is a 5.0 V output voltage with output current capability up to 200 mA. It includes a voltage monitoring
circuitry associated with a reset function. The VDD1 regulator is fully protected against overcurrent and short-circuit. It has over
temperature detection warning flags (bit VDDTEMP in MCR and interrupt registers), and overtemperature shutdown with
hysteresis.
V2 REGULATOR
V2 Regulator circuitry is designed to drive an external path transistor increasing output current flexibility. Two pins are used
to achieve the flexibility. Those pins are V2 and V2 control. The output voltage is 5.0 V and is realized by a tracking function of
the VDD1 regulator. The recommended ballast transistor is MJD32C. Other transistors can be used; however, depending upon
the PNP gain an external resistor-capacitor network might be connected. The V2 is the supply input for the CAN cell. The state
of V2 is reported in the IOR (bit V2LOW set to 1 if V2 is below 4.5 V typical).
HS1 VBAT SWITCH OUTPUT
The HS1 output is a 2.0
typical switch from the VSUP pin. It allows the supply of external switches and their associated pull-
up or pull-down circuitry, in conjunction with the wake-up input pins, for example. Output current is limited to 200 mA and HS1 is
protected against short-circuit and has an overtemperature shutdown (bit HS1OT in IOR and bit HS1OT-V2LOW in INT register).
The HS1 output is controlled from the internal register and the SPI. Because of an internal timer, it can be activated at regular
intervals in Sleep and Stop modes. It can also be permanently turned on in Normal or Standby modes to drive loads or supply
peripheral components. No internal clamping protection circuit is implemented, thus a dedicated external protection circuit is
required in case of inductive load drive.
BATTERY FALL EARLY WARNING
Refer to the discussion under the heading: Device Supply.
INTERNAL CLOCK
The device has an internal clock used to generate all timings (Reset, Watchdog, Cyclic Wake-up, Filtering Time, etc.). Two
oscillators are implemented. A high accuracy (±12 percent) used in Normal Request, Normal and Standby modes, and a low
accuracy (±30 percent) used in Sleep and Stop modes.
OPERATIONAL MODES
FUNCTIONAL MODES
The device has four primary operation modes:
1. Standby mode
2. Normal mode
3. Stop mode
4. Sleep mode
All modes are controlled by the SPI. An additional temporary mode called Normal Request mode is automatically accessed
by the device after reset or wake-up from Stop mode. A Reset (RST) mode is also implemented. Special modes and configuration
are possible for debug and program MCU flash memory.
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