SUPPLEMENTAL APPLICATION NOTES Analysis: CAN Frame" />
參數(shù)資料
型號(hào)： KIT33989DWEVB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 51/72頁(yè)
文件大小： 0K
描述： KIT EVAL 33989DW HS SBC
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，CAN 控制器
嵌入式： 是，MCU，8 位
已用 IC / 零件： MC33989
主要屬性： CAN 2.0 系統(tǒng)基礎(chǔ)芯片（SBC），SPI 接口，2 低壓降穩(wěn)壓器
次要屬性： 故障檢測(cè)，睡眠和待機(jī)模式
已供物品： 板，CD
相關(guān)產(chǎn)品： MC33989DWR2CT-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DWR2TR-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DW-ND - IC SYSTEM BASE W/CAN 28-SOIC
Analog Integrated Circuit Device Data
Freescale Semiconductor
55
33989
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
Analysis: CAN Frame with 11 Bits of Identifier Field at 1
Figure 42 is the calculation for the TCAN time with only “1” in the identifier field.
Figure 42. CAN Frame with 11 Bits of Identifier Field at 1
Analysis: CAN Frame with 11 Bits of Identifier Field at 0
Figure 43 is the calculation for the TCAN time with only “0” in the identifier field.
Figure 43. CAN Frame with 11 Bits of Identifier Field at 0
FAILURE ON V2 SUPPLY, CAN BUS LINES AND TX PIN
V2LOW
In order to have proper operation of the CAN interface, V2 must be ON. Two case can be considered:
V2 is connected with an external ballast: in case of a V2 over load condition, the flag V2LOW is set in to the SBC IOR
register. This flag is set when V2 is below the 4.0 V typical. An interrupt can also be triggered upon a V2LOW event. When
V2 is low, the CAN interface cannot operate.
V2 is connected to V1 (no ballast transistor used): V2 will be supplied by the V1 voltage. In case V1 is in an undervoltage
condition (ex V1 below the V1 under voltage reset, typ 4.6 V), the device will enter the reset mode. The V2LOW flag will
also be set. In this case, the reset pin is active, and the MCU will not send or receive any CAN messages.
TX Permanent Dominant
A TX permanent dominant condition is detected by the CAN interface and leads to a disable of the CAN driver. The TX
permanent dominant is detected if TX stays in dominant (TX low) from more than 360
s typical. The driver is automatically re-
enabled when TX goes to a high level again. When a TX permanent dominant is detected, a bit is set into the SPI register, (bit
D2 named TXF in the CAN register). This bit is latched. In order to clear the bit, two conditions are necessary:
No longer “TX permanent failure” AND
CAN register read operation.
An interrupt can be enabled.The GFAIL flag in the MCR register will also be set.
SOF
5 recessive bits
Stuff bit
5 recessive bits
Stuff bit 1 recessive bit
13 bits are needed to wake-up the SBC.
If the minimum baud rate is used (60 KBaud), TCAN = 16.7 μs*13= 217.1 μs
If 250 KBaud is used: TCAN = 4μs *13= 52 μs
SBC wakes up
TCAN
SOF 4 dominant bits
Stuff bit
5 dominant bits
Stuff bit
17 bits are needed to wake-up the SBC.
If the minimum baud rate is used (60 KBaud), TACN = 16.7 μs*17= 284 μs
If 250 KBaud is used, TCAN = 4μs *17= 68 μs.
2 dominant bits
3 dominant bit if RTR IDE & DLC=0
SBC wakes up
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