LOGIC COMMANDS AND REGISTERS Figure 19. HS1" />
參數(shù)資料
型號: KIT33989DWEVB
廠商: Freescale Semiconductor
文件頁數(shù): 32/72頁
文件大小: 0K
描述: KIT EVAL 33989DW HS SBC
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,CAN 控制器
嵌入式: 是,MCU,8 位
已用 IC / 零件: MC33989
主要屬性: CAN 2.0 系統(tǒng)基礎(chǔ)芯片(SBC),SPI 接口,2 低壓降穩(wěn)壓器
次要屬性: 故障檢測,睡眠和待機模式
已供物品: 板,CD
相關(guān)產(chǎn)品: MC33989DWR2CT-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DWR2TR-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DW-ND - IC SYSTEM BASE W/CAN 28-SOIC
Analog Integrated Circuit Device Data
38
Freescale Semiconductor
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 19. HS1 Operation when Cyclic Sense is Selected
Low Power Mode Control Register (LPC)
This register controls:
The state of HS1 in Stop and Sleep mode (HS1 permanently off or HS1 cyclic)
Enable or disable the forced wake-up function (SBC automatic wake-up after time spend in Sleep or Stop modes, time is
defined by the TIM2 register)
Enable or disable the sense of the wake-up inputs (Lx) at sampling point of the Cyclic Sense period (LX2HS1 bit).
Refer to the Cyclic Sense Wake-up discussion for details of the LPC register setup required for proper Cyclic Sense or direct
wake-up operation.
Table 28. TIM1 Control Bits
CSP2
CSP1
CSP0
Cyclic Sense Timing (ms)
Parameter
0
5
Cyclic Sense/FWU Timing 1
0
1
10
Cyclic Sense/FWU Timing 2
0
1
0
20
Cyclic Sense/FWU Timing 3
0
1
40
Cyclic Sense/FWU Timing 4
1
0
75
Cyclic Sense/FWU Timing 5
1
0
1
100
Cyclic Sense/FWU Timing 6
1
0
200
Cyclic Sense/FWU Timing 7
1
400
Cyclic Sense/FWU Timing 8
Table 29. LPC Register
LPC
D3
D2
D1
D0
$110B
W
LX2HS1
FWU
HS1AUTO
R
Reset Value
0
0
Reset Condition
POR, NR2R
N2R,STB2RSTO2R
POR, NR2R
N2R,STB2RSTO2R
POR, NR2R
N2R,STB2RSTO2R
Table 30. LX2HS1 Control Bits
LX2HS1
Wake-up Inputs Supplied by HS1
Cyclic Sense Timing, Off Time
Cyclic Sense on Time
t
HS1
Sample
10 s
HS1 OFF
HS1 ON
Lx Sampling Point
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