LOGIC COMMANDS AND REGISTERS Four registers" />
參數(shù)資料
型號(hào)： KIT33989DWEVB
廠商： Freescale Semiconductor
文件頁數(shù)： 26/72頁
文件大小： 0K
描述： KIT EVAL 33989DW HS SBC
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，CAN 控制器
嵌入式： 是，MCU，8 位
已用 IC / 零件： MC33989
主要屬性： CAN 2.0 系統(tǒng)基礎(chǔ)芯片（SBC），SPI 接口，2 低壓降穩(wěn)壓器
次要屬性： 故障檢測(cè)，睡眠和待機(jī)模式
已供物品： 板，CD
相關(guān)產(chǎn)品： MC33989DWR2CT-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DWR2TR-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DW-ND - IC SYSTEM BASE W/CAN 28-SOIC
Analog Integrated Circuit Device Data
32
Freescale Semiconductor
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Four registers can be corrupted: MCR, RCR, CAN, and IOR registers. As examples:
write to CAN register can end up as write to MCR register, or
write to TIM1 register can end up as write to RCR register
To avoid the previously described behavior, it is recommended to write into the MCR, RCR,
CAN, and IOR registers with the expected configuration, after each RST assertion.
In the application, a RST low pulse leads to an MCU reset and a software restart. By
applying this recommendation, all registers will be written with the expected configuration.
Mode Control Register (MCR)
Table 10 provides Mode Control Register data.
Table 9. Possible Corrupted Registers In Case of RST Pulse During SPI Communication
Resulting Written register
Register
MCR
RCR
CAN
IOR
Address
$000
$001
$010
$011
Target
written
register
Register
Address
CAN
$010
X
IOR
$011
X
WUR
$100
X
TIM1/2
$101
X
LPC
$110
X
INTR
$111
X
Table 10. MCR Register
MCR
D3
D2
D1
D0
$000B
W
—
MCTR2
MCTR1
MCTR0
R
BATFAIL (31)
VDDTEMP
GFAIL
WDRST
Reset Value
—
0
Reset Condition
—
POR, RESET
Notes
31.
Bit BATFAIL cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0 V.
Table 11. MCR Control Bits
MCTR2
MCTR1
MCTR0
SBC Mode
Description
0
Enter/Exit Debug Mode
To enter/exit Debug Mode, refer to detail
Debug Mode: Hardware and Software Debug...
0
1
Normal
—
0
1
0
Standby
—
0
1
Stop, Watchdog OFF (32)
—
0
1
Stop, Watchdog ON (32)
—
1
0
Sleep (33)
—
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