LOGIC COMMANDS AND REGISTERS NOTE: For SPI " />
參數(shù)資料
型號(hào)： KIT33989DWEVB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 25/72頁(yè)
文件大小： 0K
描述： KIT EVAL 33989DW HS SBC
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，CAN 控制器
嵌入式： 是，MCU，8 位
已用 IC / 零件： MC33989
主要屬性： CAN 2.0 系統(tǒng)基礎(chǔ)芯片（SBC），SPI 接口，2 低壓降穩(wěn)壓器
次要屬性： 故障檢測(cè)，睡眠和待機(jī)模式
已供物品： 板，CD
相關(guān)產(chǎn)品： MC33989DWR2CT-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DWR2TR-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DW-ND - IC SYSTEM BASE W/CAN 28-SOIC
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
NOTE: For SPI Operation
In case a low pulse is asserted by the device on the RST output pin during a SPI message,
the SPI message can be corrupted. An RST low pulse is asserted in 2 cases:
Case 1: W/D refresh issue: The MCU does not perform the SPI watchdog refresh command
before the expiration of the timeout (in Normal mode or Normal Request mode and if the
“Timeout watchdog” option is selected), or the SPI watchdog refresh command is performed
in the closed window (in Normal mode and if “Window watchdog” option is selected).
Case 2: VDD undervoltage condition: VDD falls below the VDD undervoltage threshold.
Message corruption means that the targeted register address can be changed, and another
register is written. Table 9 shows the various cases and impacts on SPI register address:
SBC Reset:
Power-On Reset POR
SBC Mode Transition: NR2R - Normal Request to Reset Mode
NR2N - Normal Request to Normal Mode
NR2STB - Normal Request to Standby
Mode
N2R - Normal to Reset Mode
STB2R - Standby to Reset Mode
STO2R - Stop to Reset Mode
STO2NR - Stop to Normal Request
SBC Mode:
RESET - SBC in Reset Mode
Table 8. List of Registers
Name
Address
Description
Comment and Use
MCR
$000
Mode Control Register
Write: Control of Normal, Standby, Sleep, Stop, Debug Modes
Read: BATFAIL flag and other status bits and flags
RCR
$001
Reset Control Register
Write: Configuration for reset voltage level, Safe bit, Stop mode
Read: CAN wake-up and CAN failure status bits
CAN
$010
CAN Control Register
Write: CAN module control: TX/RX and Sleep modes, slope control, wake
enable/disable
Read: CAN wake-up and CAN failure status bits
IOR
$011
I/O Control Register
Write: HS1 (High Side switch) control in Normal and Standby mode
Read: HS1 over temp bit, VSUP and V2 Low status
WUR
$100
Wake-up Input
Register
Write: Control of wake-up input polarity
Read: Wake-up input and real time LX input state
TIM
$101
Timing Register
Write: TIM1, Watchdog timing control, window, or Timeout mode
Write: TIM2, Cyclic sense and force wake-up timing selection
LPC
$110
Low Power Mode
Control Register
Write: Control HS1 periodic activation in Sleep and Stop modes, force
wake-up
INT
$111
Interrupt Register
Write: Interrupt source configuration
Read: INT source
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