KS8695P Micrel Reset Circuit Diagram VCC R C Power On Reset C" />
參數(shù)資料
型號: KS8695P-EVAL
廠商: Micrel Inc
文件頁數(shù): 10/40頁
文件大?。?/td> 0K
描述: BOARD EVAL EXPERIMENT KS8695P
標準包裝: 1
其它名稱: 576-1002
M9999-081805
18
August 2005
KS8695P
Micrel
Reset Circuit Diagram
VCC
R
C
Power On Reset Circuit
Manual
push button
switch
RESETN
A17
D1
WRSTO
EROEN/
WRSTPLS
R
To Memory
Set WRSTO to
Active Low
To System
System Reset
U17
T17
KS8695P
VCC
Figure 4. Example of a Reset Circuit
VCC
R
10k
D2
C
10F
D1
CPU/FPGA
RST_OUT_n
KS8695P
RST
Figure 5. Recommended circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C,and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/
FPGA provides warm reset after power up
Following pins have second function as factory test of chip
Conguration
Pin Name
Pin #
Setting
Chip Test Enable
TESTEN
F17
‘0’ = normal operation
‘1’ = factory reserved. Used for
factory test of chip and affects all
signals listed in this table.
ERWEN0/TESTACK
M17
ERWEN1/TESTREQB
N17
ERWEN2/TESTREQA
P17
ERWEN3/TICTESTTENN
R17
UCTSN/BISTEN
M14
UDCDN/SCANEN
L15
URIN/TSTRST
L14
TEST1
M4
TEST2
F4
Table 2. Conguration Pins
Reset
The KS8695P has a single reset input that can be driven by a system reset circuit or a simple power on reset circuit. The
KS8695P also features a reset output (WRSTO) that can be used to reset other devices in the system. WRSTO can be
congured as either an active high reset or an active low reset through a strap-in option on pin U17, as shown in Table 1.
The KS8695P also has a built in watchdog timer. When the watchdog timer is programmed and the timer setting expires, the
KS8695P resets itself and also asserts WRSTO to reset the other devices in the system. Figure 4 shows a typical system
using the KS8695P WRSTO as the system reset.
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