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參數(shù)資料
| 型號(hào)： | KS8695P-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 20/40頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL EXPERIMENT KS8695P |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 其它名稱： | 576-1002 |
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M9999-081805
27
August 2005
KS8695P
Micrel
General Purpose I/O Pins (continued)
Pin
Name
I/O Type(1)
Description
C15
PAD2
I/O
32-Bit PCI address and data (continued from previous page).
A15
PAD1
A16
PAD0
A6
CBEN3
I/O
PCI commands and byte enable. Active low.
B9
CBEN2
The PCI command and byte enable signals are multiplexed on the same pins. During
A11
CBEN1
the rst clock cycle of a PCI transaction, the CBEN bus contains the command for
D14
CBEN0
the transaction. The PCI transaction consists of the address phases and one or more
data phases. During the data phases of the transaction, the bus carries the byte
enable for the current data phases.
C8
PAR
I/O
Parity. PCI bus parity is even across PAD[31:0] and CBEN[3:0]. The KS8695P gener-
ates PAR during the address phase and write data phases as a bus master and
during read data phases as a target. It checks for correct PAR during the read data
phase as a bus master, during every address phase as a bus slave, and during write
data phases as a target.
D10
FRAMEN
I/O
PCI bus frame signal. Active low. FRAMEN is an indication of an active PCI bus
cycle. It is asserted at the beginning of a PCI transaction, i.e. the address phase, and
deasserted before the nal transfer of the data phase of the transaction.
A9
IRDYN
I/O
PCI initiator ready signal. Active low. This signal is asserted by a PCI master to
indicate a valid data phase on the PAD bus during data phases of a write transaction.
During a read transaction, it indicates that the master is ready to accept data from the
target. A target monitors the IRDYN signal when a data phase is completed on any
rising edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles
are inserted until both IRDYN and TRDYN are asserted together.
C10
TRDYN
I/O
PCI target ready signal. Active low. This signal is asserted by a PCI slave to
indicate a valid data phase on the PAD bus during a read transaction. During a write
transaction, it indicates that the slave is ready to accept data from the target. A PCI
initiator monitors the TRDYN signal when a data phase is completed on any rising
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
inserted until both IRDYN and TRDYN are asserted together.
C11
DEVSELN
I/O
PCI device select signal. Active low. This signal is asserted when the KS8695P is
selected as a target during a bus transaction. When the KS8695P is the initiator of the
current bus access, it expects the target to assert DEVSELN within ve PCI bus
cycles, conrming the access. If the target does not assert DEVSELN within the
required bus cycles, the KS8695P aborts the bus cycle. To meet the timing require-
ment, the KS8695P asserts this signal in a medium speed decode timing. ( two bus
cycles).
D7
IDSEL
I
Initialization device select. Active high. It is used as a chip select during congura-
tion read and write transactions.
D11
STOPN
I/O
PCI stop signal. Active low. This signal is asserted by the PCI target to indicate to
the bus master that it is terminating the current transaction. The KS8695P responds
to
the assertion of STOPN when it is the bus master, either to disconnect, retry, or abort
the transaction.
B11
PERRN
I/O
PCI parity error signal. Active low. The KS8695P asserts PERRN when it checks
and detects a bus parity error. When it generates the PAR output, the KS8695P
monitors for any reported parity error on PERRN. When the KS8695P is the bus
master and a parity error is detected, the KS8695P sets error bits in the control status
registers. It completes the current data burst transaction, and then stops the opera-
tion. After the host clears the system error, the KS8695P continues its operation.
A10
SERRN
O
PCI system error signal. Active low. If an address parity error is detected, the
KS8695P asserts the SERRN signal two clocks after the failing address.
E4
M66EN
I
PCI 66MHz enable. When asserted, this signal indicates the PCI bus segment is
operating at 66MHz. This pin is mainly used in guest bridge mode when the PCLK is
driven by an external host bridge.
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
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| KS8695PI | 功能描述:IC ARM9 W/MMU 5PORT 289-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KS8695P-MDP-EVAL | 功能描述:EVAL KIT EXPERIMENTAL KS8695PMPD RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| KS8695P-MMB-EVAL | 功能描述:BOARD EVAL MULTIMEDIA KS8695P RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| KS8695PX | 功能描述:IC SWITCH 10/100 1PORT 289PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KS8695PXA3 | 功能描述:IC ARM9 W/MMU 5PORT 289-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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