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參數(shù)資料
| 型號： | KS8695P-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 16/40頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL EXPERIMENT KS8695P |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 其它名稱： | 576-1002 |
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M9999-081805
23
August 2005
KS8695P
Micrel
Signal Descriptions by Group
Clock and Reset Pins
Pin
Name
I/O Type(1)
Description
E1
XCLK1/
I
External Clock In. This signal is used as the source clock for the transmit clock of the
CPUCLK
internal MAC and PHY. The clock frequency is 25MHz ±50ppm. The XCLK1
signal is also used as the reference clock signal for the internal PLL to generate the
125MHz internal system clock.
E2
XCLK2
I
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
This is unused for a normal clock input.
M15
URTSN/
O/I
Normal Mode: UART request to send. Active low output.
CPUCLKSEL
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
mode), the internal PLL clock output is used as the CPU clock source.
CPUCLKSEL=1 (factory reserved test signal).
A17
RESETN
I
KS8695P chip reset. Active low input asserted for at least 256 system clock (40ns)
cycles to reset the KS8695P. When in the reset state, all the output pins are tri-stated
and all open drain signals are oating.
U17
WRSTO
O
Watchdog timer reset output. This signal is asserted for at least 200ms if
RESETN is asserted or when the internal watchdog timer expires.
T17
EROEN/
O/I
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low. When
WRSTPLS
asserted, this signal controls the output enable port of the specied device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
WRSTPLS=1, Active low. No default.
JTAG Interface Pins
Pin
Name
I/O Type(1)
Description
G14
TCK
I
JTAG test clock.
G15
TMS
I
JTAG test mode select.
F14
TDI
I
JTAG test data in.
F15
TDO
O
JTAG test data out.
F16
TRSTN
I
JTAG test reset. Active low.
WAN Ethernet Physical Interface Pins
Pin
Name
I/O Type(1)
Description
G1
WANTXP
O
WAN PHY transmit signal + (differential).
G2
WANTXM
O
WAN PHY transmit signal – (differential).
G3
WANRXP
I
WAN PHY receive signal + (differential).
G4
WANRXM
I
WAN PHY receive signal – (differential).
G5
WANFXSD
I
WAN ber signal detect. Signal detect input when the WAN port is operated in
100BASE-FX 100Mb ber mode. See Application Note 10.
Note:
1. I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KS8695PI | 功能描述:IC ARM9 W/MMU 5PORT 289-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KS8695P-MDP-EVAL | 功能描述:EVAL KIT EXPERIMENTAL KS8695PMPD RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| KS8695P-MMB-EVAL | 功能描述:BOARD EVAL MULTIMEDIA KS8695P RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| KS8695PX | 功能描述:IC SWITCH 10/100 1PORT 289PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KS8695PXA3 | 功能描述:IC ARM9 W/MMU 5PORT 289-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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