KS8695P Micrel General Purpose I/O Pins (continued) Pin Name I/O Type(
參數(shù)資料
型號(hào)： KS8695P-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 21/40頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL EXPERIMENT KS8695P
標(biāo)準(zhǔn)包裝： 1
其它名稱： 576-1002
August 2005
28
M9999-081805
KS8695P
Micrel
General Purpose I/O Pins (continued)
Pin
Name
I/O Type(1)
Description
D1
PCLKOUT3
O
PCI clock output 3. In host bridge mode driven as 33MHz
In guest bridge mode, this signal is reserved
C1
PCLKOUT2
O
PCI clock output 2. In host bridge mode driven as 33MHz
In guest bridge mode, this signal is reserved
B1
PCLKOUT1
O
PCI clock output 1. In host bridge mode driven as 33MHz
In guest bridge mode, this signal is reserved
A2
PCLKOUT0
O
PCI clock output 0. In host bridge mode driven as 33MHz
In guest bridge mode, this signal is reserved
B10
CLKRUNN
I/O
This is a cardbus only signal. The CLKRUNN signal is used by portable cardbus
devices to request that the system turn on the bus clock. Output is always active in
cardbus and miniPCI modes.
D2
MPCIACTN
O
MiniPCI active. This signal is asserted by the PCI device to indicate that its current
function requires full system performance. MPCIACTN is an open drain output signal.
In miniPCI mode, this signal is always low.
D3
PBMS
I
PCI bridge mode select. This selects the operating mode for the PCI bridge. When
PBMS is high, the host bridge mode is selected and the on-chip PCI bus arbiter is
enabled. When PBMS is low, the guest bridge mode is selected and the on-chip
arbiter is disabled.
Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O)
Pin
Name
I/O Type(1)
Description
T7
SDICLK
I
SDRAM Clock In: SDRAM clock input for the SDRAM memory controller interface.
U7
SDOCLK
O
System/SDRAM Clock Out: Output of the internal system clock, it is also used as the
clock signal for SDRAM interface.
P4
ADDR21/BA1
O
Address Bit 21/Bank Address Input 1: Address bit 21 for asynchronous accesses.
Bank Address Input bit 1 for SDRAM accesses.
P3
ADDR20/BA0
O
Address Bit 20/Bank Address Input 0: Address bit 20 for asynchronous accesses.
Bank Address Input bit 0 for SDRAM accesses.
M3
ADDR[19]
O
Address Bus: The 22-bit address bus (including ADDR[21:20] above) covers 4M word
M2
ADDR[18]
memory space shared by ROM/SRAM/FLASH, SDRAM, and external I/O banks.
M1
ADDR[17]
During the SDRAM cycles, the internal address bus is used to generate RAS and
N4
ADDR[16]
CAS addresses for the SDRAM. The number of column address bits in the SDRAM
N3
ADDR[15]
banks can be programmed from 8 to 11 bits via the SDRAM control registers.
N2
ADDR[14]
ADDR[12:0] are the SDRAM address and ADDR[21:20] are the SDRAM bank
N1
ADDR[13]
address. During other cycles, the ADDR[21:0] is the byte address of the data transfer.
P2
ADDR[12]
For SDRAM and FLASH/ROM/SRAM, connect all address lines, i.e. A0 to A0, A1 to
P1
ADDR[11]
A1, etc. The memory controller automatically handles address line adjustments for the
R3
ADDR[10]
8/16/32 bit accesses. For external I/O devices, the user needs to connect address
R2
ADDR[9]
lines for 8/16/32 bit accesses.
R1
ADDR[8]
T2
ADDR[7]
T1
ADDR[6]
U1
ADDR[5]
U2
ADDR[4]
T3
ADDR[3]
U3
ADDR[2]
T4
ADDR[1]
U4
ADDR[0]
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
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