參數(shù)資料
型號： KSZ8851-16MLLI TR
廠商： Micrel Inc
文件頁數(shù)： 34/84頁
文件大?。?/td> 0K
描述： IC MAC CTLR 1PORT W/BUS 48LQFP
標準包裝： 1,000
控制器類型： 以太網(wǎng)控制器，MAC/PHY
接口： 總線
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
Micrel, Inc.
KSZ8851-16MLL/MLLI
March 11, 2014
4
Revision 2.2
Contents
List of Figures.......................................................................................................................................................................... 7
List of Tables ........................................................................................................................................................................... 8
Pin Configuration..................................................................................................................................................................... 9
Pin Description ...................................................................................................................................................................... 10
Pin for Strap-In Options......................................................................................................................................................... 13
Functional Description........................................................................................................................................................... 14
Functional Overview.............................................................................................................................................................. 14
Rx unused block disabled............................................................................................................................................. 14
Wake-up Packet ........................................................................................................................................................... 16
Physical Layer Transceiver (PHY) ........................................................................................................................................ 17
Straight Cable ............................................................................................................................................................... 18
Crossover Cable ........................................................................................................................................................... 19
Access .......................................................................................................................................................................... 21
Usage ........................................................................................................................................................................... 21
Frame Queue (RXQ) Frame Format ............................................................................................................................ 29
EEPROM Interface ....................................................................................................................................................... 31
CPU Interface I/O Registers.................................................................................................................................................. 33
I/O Registers................................................................................................................................................................. 33
Internal I/O Registers Space Mapping ......................................................................................................................... 33
CIDER ................................................................................................................................................................................... 37
0x887x................................................................................................................................................................................... 37
Reserved ............................................................................................................................................................................... 38
Do Not Care .......................................................................................................................................................................... 38
None ...................................................................................................................................................................................... 38
Register Map: MAC, PHY and QMU ..................................................................................................................................... 39
Bit Type Definition ........................................................................................................................................................ 39
0x00 – 0x07: Reserved................................................................................................................................................. 39
Chip Configuration Register (0x08 – 0x09): CCR ........................................................................................................ 39
0x0A – 0x0F: Reserved ................................................................................................................................................ 39
Host MAC Address Registers: MARL, MARM and MARH ........................................................................................... 40
Host MAC Address Register Low (0x10 – 0x11): MARL.............................................................................................. 40
Host MAC Address Register Middle (0x12 – 0x13): MARM......................................................................................... 40
Host MAC Address Register High (0x14 – 0x15): MARH ............................................................................................ 40
0x16 – 0x1F: Reserved ................................................................................................................................................ 40
On-Chip Bus Control Register (0x20 – 0x21): OBCR .................................................................................................. 41
EEPROM Control Register (0x22 – 0x23): EEPCR ..................................................................................................... 41
Memory BIST Info Register (0x24 – 0x25): MBIR ........................................................................................................ 42
Global Reset Register (0x26 – 0x27): GRR ................................................................................................................. 42
0x28 – 0x29: Reserved................................................................................................................................................. 42
Wakeup Frame Control Register (0x2A – 0x2B): WFCR ............................................................................................. 43
0x2C – 0x2F: Reserved ................................................................................................................................................ 43
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 ...................................................................................... 43
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 ...................................................................................... 43
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 .............................................................................. 44
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 .............................................................................. 44
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 .............................................................................. 44
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3.............................................................................. 44
0x3C – 0x3F: Reserved ................................................................................................................................................ 44
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