參數(shù)資料
型號: KSZ8851-16MLLI TR
廠商: Micrel Inc
文件頁數(shù): 67/84頁
文件大?。?/td> 0K
描述: IC MAC CTLR 1PORT W/BUS 48LQFP
標(biāo)準(zhǔn)包裝: 1,000
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8851-16MLL/MLLI
March 11, 2014
7
Revision 2.2
List of Figures
Figure 2. 48-Pin LQFP ........................................................................................................................................................... 9
Figure 3. Typical Straight Cable Connection ........................................................................................................................ 18
Figure 4. Typical Crossover Cable Connection .................................................................................................................... 19
Figure 5. Auto Negotiation And Parallel Operation ............................................................................................................... 20
Figure 6. Ksz8851-16mll 8-Bit And 16-Bit Data Bus Connections........................................................................................ 25
Figure 8. Host Rx Single Or Multiple Frames In Auto-Dequeue Flow Diagram.................................................................... 30
Figure 9. Phy Port 1 Near-End (Remote) And Host Far-End (Local) Loopback Paths......................................................... 32
Figure 10. Asynchronous Cycle ............................................................................................................................................ 75
Figure 11. Auto Negotiation Timing....................................................................................................................................... 76
Figure 12. Reset Timing........................................................................................................................................................ 77
Figure 13. Eeprom Read Cycle Timing Diagram .................................................................................................................. 78
Figure 14. Recommended Reset Circuit .............................................................................................................................. 79
Figure 15. Recommended Circuit For Interfacing with Cpu/Fpga Reset ............................................................................. 79
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