參數(shù)資料
型號: KSZ8851-16MLLI TR
廠商: Micrel Inc
文件頁數(shù): 4/84頁
文件大小: 0K
描述: IC MAC CTLR 1PORT W/BUS 48LQFP
標準包裝: 1,000
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8851-16MLL/MLLI
March 11, 2014
12
Revision 2.2
Pin Description (Continued)
Pin Number
Pin Name
Type
Pin Function
36
SD9
I/O (PD)
Shared Data Bus bit 9. Data D9 access when CMD=0. Do Not Care when CMD=1. This
pin must be tied to GND in 8-bit bus mode.
37
DGND
GND
Digital ground
38
VDD_IO
P
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
39
SD8
I/O (PD)
Shared Data Bus bit 8. Data D8 access when CMD=0. Do Not Care when CMD=1. This
pin must be tied to GND in 8-bit bus mode.
40
SD7
I/O (PD)
Shared Data Bus bit 7. Data D7 access when CMD=0. Address A7 access when CMD=1.
41
SD6
I/O (PD)
Shared Data Bus bit 6. Data D6 access when CMD=0. Address A6 access when CMD=1.
42
SD5
I/O (PD)
Shared Data Bus bit 5. Data D5 access when CMD=0. Address A5 access when CMD=1.
43
SD4
I/O (PD)
Shared Data Bus bit 4. Data D4 access when CMD=0. Address A4 access when CMD=1.
44
SD3
I/O (PD)
Shared Data Bus bit 3. Data D3 access when CMD=0. Address A3 access when CMD=1.
45
SD2
I/O (PD)
Shared Data Bus bit 2. Data D2 access when CMD=0. Address A2 access when CMD=1.
46
VDD_IO
P
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
47
SD1
I/O (PD)
Shared Data Bus bit 1. Data D1 access when CMD=0. In 8-bit mode, this is address A1
access when CMD=1. In 16-bit mode, this is “Do Not Care” when CMD=1.
48
SD0
I/O (PD)
Shared Data Bus bit 0. Data D0 access when CMD=0. In 8-bit mode, this is address A0
access when CMD=1. In 16-bit mode, this is “Do Not Care” when CMD=1.
Legend:
P = Power supply
GND = Ground
I/O = Bi-directional
I = Input
O = Output.
IPD = Input with internal pull-down (58K ±30%).
IPU = Input with internal pull-up (58K ±30%).
OPD = Output with internal pull-down (58K ±30%).
OPU = Output with internal pull-up (58K ±30%).
IPU/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.
IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.
I/O (PD) = Input/Output with internal pull-down (58K ±30%).
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