參數(shù)資料
型號(hào)： KSZ8851-16MLLI TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 73/84頁(yè)
文件大小： 0K
描述： IC MAC CTLR 1PORT W/BUS 48LQFP
標(biāo)準(zhǔn)包裝： 1,000
控制器類型： 以太網(wǎng)控制器，MAC/PHY
接口： 總線
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
2002 Microchip Technology Inc.
DS30325B-page 73
PIC16F7X
10.2
USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one START bit, eight or nine data
bits, and one STOP bit). The most common data format
is 8-bits. An on-chip, dedicated, 8-bit baud rate gener-
ator can be used to derive standard baud rate frequen-
cies from the oscillator. The USART transmits and
receives the LSb first. The USART’s transmitter and
receiver are functionally independent, but use the
same data format and baud rate. The baud rate gener-
ator produces a clock, either x16 or x64 of the bit shift
rate, depending on bit BRGH (TXSTA<2>). Parity is not
supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchro-
nous mode is stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
10.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data by firmware. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new data
from the TXREG register (if available). Once the TXREG
register transfers the data to the TSR register, the
TXREG register is empty. One instruction cycle later,
flag bit TXIF (PIR1<4>) and flag bit TRMT (TXSTA<1>)
are set. The TXIF interrupt can be enabled/disabled by
setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF
will be set, regardless of the state of enable bit TXIE and
cannot be cleared in software. It will reset only when new
data is loaded into the TXREG register. While flag bit
TXIF indicates the status of the TXREG register, another
bit TRMT (TXSTA<1>) shows the status of the TSR reg-
ister. Status bit TRMT is a read only bit, which is set one
instruction cycle after the TSR register becomes empty,
and is cleared one instruction cycle after the TSR regis-
ter is loaded. No interrupt logic is tied to this bit, so the
user has to poll this bit in order to determine if the TSR
register is empty.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur until
the TXREG register has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 10-2). The transmission can also be started by
first loading the TXREG register and then setting enable
bit TXEN. Normally, when transmission is first started,
the TSR register is empty. At that point, transfer to the
TXREG register will result in an immediate transfer to
TSR, resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 10-3). Clearing enable
bit TXEN during a transmission will cause the transmis-
sion to be aborted and will reset the transmitter. As a
result, the RC6/TX/CK pin will revert to hi-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be writ-
ten before writing the 8-bit data to the TXREG register.
This is because a data write to the TXREG register can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). In such a case, an incor-
rect ninth data bit may be loaded in the TSR register.
FIGURE 10-1:
USART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
TXIF
TXIE
Interrupt
TXEN
Baud Rate CLK
SPBRG
Baud Rate Generator
TX9D
MSb
LSb
Data Bus
TXREG Register
TSR Register
(8)
0
TX9
TRMT
SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
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