- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1931 > KSZ8851-16MLLJ (Micrel Inc)IC CTLR MAC 1PORT NON-PCI 48LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | KSZ8851-16MLLJ |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 22/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTLR MAC 1PORT NON-PCI 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/PHY |
| 接口： | 總線 |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 576-3629 KSZ8851-16MLLJ-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
29
M9999-030210-1.0
Bit
Description
15-11
Reserved.
10-0
TXBC Transmit Byte Count
Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer memory for better
utilization of the packet memory.
Note: The hardware behavior is unknown if an incorrect byte count information is written to this field. Writing a 0
value to this field is not permitted.
Table 7. Transmit Byte Count Format
The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed by a
variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8851-16MLLJ does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted
by the KSZ8851-16MLLJ. It is treated transparently as data both for transmit operations.
Frame Transmitting Path Operation in TXQ
This section describes the typical register settings for transmitting packets from host processor to KSZ8851-16MLLJ with
generic bus interface. User can use the default value for most of the transmit registers. The following Table 8 describes all
registers which need to be set and used for transmitting single or multiple frames.
Register Name
[bit](offset)
Description
TXCR[3:0](0x70)
TXCR[8:5](0x70)
Set transmit control function as below:
Set bit 3 to enable transmitting flow control. Set bit 2 to enable transmitting padding.
Set bit 1 to enable transmitting CRC. Set bit 0 to enable transmitting block operation.
Set transmit checksum generation for ICMP, UDP, TCP and IP packet.
TXMIR[12:0](0x78)
The amount of free transmit memory available is represented in units of byte. The TXQ memory (6
KByte) is used for both frame payload and control word.
TXQCR[0](0x80)
For single frame to transmit, set this bit 0 = 1(manual enqueue). the KSZ8851-16MLLJ will enable
current TX frame prepared in the TX buffer is queued for transmit, this is only transmit one frame at a
time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit
to be cleared before setting up another new TX frame.
TXQCR[1](0x80)
When this bit is written as 1, the KSZ8851-16MLLJ will generate interrupt (bit 6 in ISR register) to CPU
when TXQ memory is available based upon the total amount of TXQ space requested by CPU at
TXNTFSR (0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit
to be cleared before set to 1 again
TXQCR[2](0x80)
For multiple frames to transmit, set this bit 2 = 1 (auto-enqueue). the KSZ8851-16MLLJ will enable
current all TX frames prepared in the TX buffer are queued to transmit automatically.
RXQCR[3](0x82)
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data
frame)
TXFDPR[14](0x84)
Set bit 14 to enable TXQ transmit frame data pointer register increments automatically on accesses to
the data register.
IER[14][6](0x90)
Set bit 14 to enable transmit interrupt in Interrupt Enable Register
Set bit 6 to enable transmit space available interrupt in Interrupt Enable Register.
ISR[15:0](0x92)
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
TXNTFSR[15:0](0x9E)
The host CPU is used to program the total amount of TXQ buffer space which is required for next total
transmit frames size in double-word count.
Table 8. Registers Setting for Transmit Function Block
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KSZ8851-32MQLI | IC CTLR MAC/PHY NON PCI 128PQFP |
| KSZ8851-32MQL | IC CTLR MAC/PHY NON PCI 128PQFP |
| KSZ8851SNLI TR | IC ETHERNET CTLR 1PORT PCI 32MLF |
| KSZ8862-16MQL | IC SWITCH 10/100 16BIT 128-PQFP |
| KSZ8862-32MQL | IC ETHERNET SW 2PORT BUS 128PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8851-16MLLJ_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface |
| KSZ8851-16MLLU | 功能描述:以太網(wǎng) IC Single-Port Ethernet Controller (Automotive Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8851-16MLLU TR | 功能描述:以太網(wǎng) IC Single-Port Ethernet Controller (Automotive Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8851-16MQL | 功能描述:以太網(wǎng) IC Single Ethernet Port + Generic (16-bit) Bus Interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8851-16MQL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 Single Ethernet Port + Generic (16-bit) Bus Interface(Lead Free) Eval Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。