參數(shù)資料
型號(hào): KSZ8851-16MLLJ
廠商: Micrel Inc
文件頁數(shù): 29/90頁
文件大小: 0K
描述: IC CTLR MAC 1PORT NON-PCI 48LQFP
標(biāo)準(zhǔn)包裝: 250
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 576-3629
KSZ8851-16MLLJ-ND
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
35
M9999-030210-1.0
Driver Routine for Receive Packet from KSZ8851-16MLLJ to Host Processor
The software driver receives data packet frames from the KSZ8851-16MLLJ device either as a result of polling or an
interrupt based service. When an interrupt is received, the OS invokes the interrupt service routine that is in the interrupt
vector table.
If your system has OS support, to minimize interrupt lockout time, the interrupt service routine should handle at interrupt
level only those tasks that require minimum execution time, such as error checking or device status change. The routine
should queue all the time-consuming work to transfer the packet from the KSZ8851-16MLLJ RXQ into system memory at
task level. The following Figure 9 shows the step-by-step for receive packets from KSZ8851-16MLLJ to host processor.
Note: Each DMA read operation from the host CPU to read RXQ frame buffer, the first read data (byte in 8-bit bus mode,
word in 16-bit bus mode and double word in 32-bit bus mode) is dummy data and must be discarded by host CPU.
Afterward, host CPU must read each frame data to align with double word boundary at end. For example, the host CPU
has to read up to 68 bytes if received frame is 65 bytes.
Figure 9. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram
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相關(guān)代理商/技術(shù)參數(shù)
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KSZ8851-16MLLJ_10 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
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