參數(shù)資料
型號(hào): KSZ8851-16MLLJ
廠商: Micrel Inc
文件頁數(shù): 70/90頁
文件大?。?/td> 0K
描述: IC CTLR MAC 1PORT NON-PCI 48LQFP
標(biāo)準(zhǔn)包裝: 250
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 576-3629
KSZ8851-16MLLJ-ND
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
72
M9999-030210-1.0
PHY 1 MII-Register Basic Status Register (0xE6 – 0xE7): P1MBSR
This register contains the MII register status for the chip function.
Bit
Default
R/W
Description
Bit is same as:
15
0
RO
T4 Capable
1 = 100 BASE-T4 capable.
0 = not 100 BASE-T4 capable.
14
1
RO
100 Full Capable
1 = 100BASE-TX full-duplex capable.
0 = not 100BASE-TX full duplex.capable.
13
1
RO
100 Half Capable
1= 100BASE-TX half-duplex capable.
0= not 100BASE-TX half-duplex capable.
12
1
RO
10 Full Capable
1 = 10BASE-T full-duplex capable.
0 = not 10BASE-T full-duplex capable.
11
1
RO
10 Half Capable
1 = 10BASE-T half-duplex capable.
0 = not 10BASE-T half-duplex capable.
10-7
0x0
RO
Reserved.
6
0
RO
Preamble suppressed
Not supported.
5
0
RO
AN Complete
1 = auto-negotiation complete.
0 = auto-negotiation not completed.
Bit 6 in P1SR
4
0
RO
Reserved
3
1
RO
AN Capable
1 = auto-negotiation capable.
0 = not auto-negotiation capable.
2
0
RO
Link Status
1 = link is up; 0 = link is down.
Bit 5 in P1SR
1
0
RO
Jabber test
Not supported.
0
RO
Extended Capable
1 = extended register capable.
0 = not extended register capable.
PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR
This register contains the PHY ID (low) for the chip.
Bit
Default
R/W
Description
15-0
0x1430
RO
PHYID Low
Low order PHYID bits.
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