參數(shù)資料
型號(hào): KSZ8851-16MLLJ
廠商: Micrel Inc
文件頁數(shù): 25/90頁
文件大?。?/td> 0K
描述: IC CTLR MAC 1PORT NON-PCI 48LQFP
標(biāo)準(zhǔn)包裝: 250
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 576-3629
KSZ8851-16MLLJ-ND
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
31
M9999-030210-1.0
Figure 7. Host TX Single Frame in Manual Enqueue Flow Diagram
Host receives an Ethernet pkt from
upper layer and prepares transmit pkt
data (data, data_length, frame ID).
The transmit queue frame format is
shown in Table 5
Check if KSZ8851M TXQ
Memory size is available for this
transmit pkt?
(Read TXMIR Reg)
Write an “1” to RXQCR[3] reg to enable
TXQ write access, then Host starts
write transmit data (control word, byte
count and pkt data) to TXQ memory.
This is moving transmit data from Host
to KSZ8851M TXQ memory until whole
pkt is finished
Write an “0” to RXQCR[3] reg to end
TXQ write access
Write an “1” to TXQCR[0] reg to issue a
transmit command (manual-enqueue)
to the TXQ. The TXQ will transmit this
pkt data to the PHY port
Option to Read ISR[14] reg, it indicates
that the TXQ has completed to transmit
at least one pkt to the PHY port, then
Write “1” to clear this bit
Yes
No
Write the total amount of TXQ buffer
space which is required for next
transmit frame size in double-word
count in TXNTFSR[15:0] register
Set bit 1=1 in TXQCR register to
enable the TXQ memory available
monitor
Wait for interrupt
and check if the bit 6=1
(memory space available)
in ISR register
?
Yes
No
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KSZ8851-16MLLJ_10 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
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