參數(shù)資料
型號: KSZ8851-16MLLJ
廠商: Micrel Inc
文件頁數(shù): 5/90頁
文件大?。?/td> 0K
描述: IC CTLR MAC 1PORT NON-PCI 48LQFP
標準包裝: 250
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 576-3629
KSZ8851-16MLLJ-ND
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
13
M9999-030210-1.0
Pin Description (Continued)
Pin Number
Pin Name
Type
Pin Function
12
CSN
Ipu
Chip Select Not
Chip select for the shared data bus access enable, active Low.
13
AGND
Gnd
Analog ground
14
VDD_A1.8
P
1.8V analog power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is
1.8V, this pin must be supplied power from the same source as pins 27, 38 and 46
(VDD_IO) with appropriate filtering.
15
EECS
Opd
EEPROM Chip Select
This signal is used to select an external EEPROM device.
16
RXP1
I/O
Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential).
17
RXM1
I/O
Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential).
18
AGND
Gnd
Analog ground.
19
TXP1
I/O
Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential).
20
TXM1
I/O
Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential).
21
VDD_A3.3
P
3.3V analog VDD input power supply with well decoupling capacitors.
22
ISET
O
Set physical transmits output current.
Pull-down this pin with a 3.01K 1% resistor to ground.
23
RSTN
Ipu
Reset Not
Hardware reset pin (active Low). This reset input is required minimum of 10ms low after
stable supply voltage 3.3V.
24
X1
I
25
X2
O
25MHz crystal or oscillator clock connection.
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant
oscillator and X2 is a no connect.
Note: Clock requirement is ±50ppm for either crystal or oscillator.
26
DGND
Gnd
Digital ground
27
VDD_IO
P
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
28
DGND
Gnd
Digital ground
29
VDD_D1.8
P
1.8V digital power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is
1.8V, this pin must be supplied power from the same source as pins 27, 38 and 46
(VDD_IO) with appropriate filtering.
30
SD15
I/O (pd)
Shared Data Bus bit 15. Data D15 access when CMD=0. Byte Enable 3 at double-word
boundary access (BE3, 4th byte enable and active high) in 16-bit mode when CMD=1.
This pin must be tied to GND in 8-bit bus mode.
31
SD14
I/O (pd)
Shared Data Bus bit 14. Data D14 access when CMD=0. Byte Enable 2 at double-word
boundary access (BE2, 3rd byte enable and active high) in 16-bit mode when CMD=1.
This pin must be tied to GND in 8-bit bus mode.
32
SD13
I/O (pd)
Shared Data Bus bit 13. Data D13 access when CMD=0. Byte Enable 1 at double-word
boundary access (BE1, 2nd byte enable and active high) in 16-bit mode when CMD=1.
This pin must be tied to GND in 8-bit bus mode.
33
SD12
I/O (pd)
Shared Data Bus bit 12. Data D12 access when CMD=0. Byte Enable 0 at double-word
boundary access (BE0, 1st byte enable and active high) in 16-bit mode when CMD=1.
This pin must be tied to GND in 8-bit bus mode.
34
SD11
I/O (pd)
Shared Data Bus bit 11. Data D11 access when CMD=0. Don’t care when CMD=1. This
pin must be tied to GND in 8-bit bus mode.
35
SD10
I/O (pd)
Shared Data Bus bit 10. Data D10 access when CMD=0. Don’t care when CMD=1. This
pin must be tied to GND in 8-bit bus mode.
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