參數(shù)資料
型號: KSZ8851-16MLLJ
廠商: Micrel Inc
文件頁數(shù): 4/90頁
文件大小: 0K
描述: IC CTLR MAC 1PORT NON-PCI 48LQFP
標準包裝: 250
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 576-3629
KSZ8851-16MLLJ-ND
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
12
M9999-030210-1.0
Pin Description
Pin Number
Pin Name
Type
Pin Function
1
P1LED1
Ipu/O
2
P1LED0
Opu
Programmable LED output to indicate port activity/status.
LED is ON when output is LOW; LED is OFF when output is HIGH.
Port 1 LED indicators
1 defined as follows:
Chip Global Control Register: CGCR bit [9]
0 (Default)
1
P1LED1
100BT
ACT
P1LED0
LINK/ACT
LINK
1. Link = LED On; Activity = LED Blink; Link/Act = LED On/Blink;
Speed = LED On (100BASE-T); LED Off (10BASE-T)
Config Mode: The P1LED1 pull-up/pull-down value is latched as 16/8-bit mode during
power-up / reset. See “Strapping Options” section for details
3
PME
Opu
Power Management Event (default active low): It is asserted (low or high depends on
polarity set in PMECR register) when one of the wake-on-LAN events is detected by
KSZ8851-16MLLJ. The KSZ8851-16MLLJ is requesting the system to wake up from low
power mode.
4
INTRN
Opu
Interrupt: An active low signal to host CPU to indicate an interrupt status bit is set, this pin
need an external 4.7K pull-up resistor.
5
RDN
Ipu
Read Strobe Not
Asynchronous read strobe, active low to indicate read cycle.
6
WRN
Ipu
Write Strobe Not
Asynchronous write strobe, active low to indicate write cycle.
7
DGND
Gnd
Digital ground
8
VDD_CO1.8
P
1.8V regulator output . This 1.8V output pin provides power to pins 14 (VDD_A1.8) and 29
(VDD_D1.8) for core VDD supply.
If VDD_IO is set for 1.8V then this pin should be left floating, pins 14 (VDD_A1.8) and 29
(VDD_D1.8) will be sourced by the external 1.8V supply that is tied to pins 27, 38 and 46
(VDD_IO) with appropriate filtering.
9
EED_IO
Ipd/O
In/Out Data from/to external EEPROM.
Config Mode: The pull-up/pull-down value is latched as with/without EEPROM during
power-up / reset. See “Strapping Options” section for details
10
EESK
Ipd/O
EEPROM Serial Clock
A 4
μs (OBCR[1:0]=11 on-chip bus speed @ 25MHz) or 800ns (OBCR[1:0]=00 on-chip
bus speed @ 125MHz) serial output clock cycle to load configuration data from the serial
EEPROM.
Config Mode: The pull-up/pull-down value is latched as big/little endian mode during
power-up / reset. See “Strapping Options” section for details
11
CMD
Ipd
Command Type
This command input decides the SD[15:0] shared data bus access information.
When command input is low, the access of shared data bus is for data access in 16-bit
mode shared data bus SD[15:0] or in 8-bit mode shared data bus SD[7:0].
When command input is high, the access of shared data bus is for address A[7:2] access
at shared data bus SD[7:2], byte enable BE[3:0] at SD[15:12] and the SD[11:8] is “don’t
care” in 16-bit mode. It is for address A[7:0] access at SD[7:0] in 8-bit mode.
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