參數(shù)資料
型號： KSZ8873FLLI
廠商： Micrel Inc
文件頁數(shù)： 14/115頁
文件大?。?/td> 0K
描述： IC ETHERNET SWITCH 3PORT 64LQFP
產(chǎn)品培訓模塊： KSZ8873 Ethernet Switches
標準包裝： 160
控制器類型： 以太網(wǎng)開關控制器
接口： MII
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-LQFP（10x10）
包裝： 托盤
其它名稱： 576-3632
KSZ8873FLLI-ND
PIC16(L)F1508/9
DS41609A-page 110
Preliminary
2011 Microchip Technology Inc.
TABLE 10-3:
SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
TABLE 10-4:
SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
REGISTER 10-6:
PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0
Program Memory Control Register 2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Flash Memory Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PMCON1
—
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
PMCON2
Program Memory Control Register 2
PMADRL
PMADRL<7:0>
PMADRH
—
PMADRH<6:0>
PMDATL
PMDATL<7:0>
PMDATH
—
PMDATH<5:0>
Legend:
—
= unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
Register
on Page
CONFIG1
13:8
—
FCMEN
IESO
CLKOUTEN
BOREN<1:0>
—
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
FOSC<2:0>
CONFIG2
13:8
—
LVP
DEBUG
LPBOR
BORV
STVREN
—
7:0
—
—WRT<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
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