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參數(shù)資料
| 型號： | KSZ8873FLLI |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 45/115頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET SWITCH 3PORT 64LQFP |
| 產(chǎn)品培訓模塊： | KSZ8873 Ethernet Switches |
| 標準包裝： | 160 |
| 控制器類型： | 以太網(wǎng)開關控制器 |
| 接口： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 576-3632 KSZ8873FLLI-ND |
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Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
35
Revision 1.6
Table 8 depicts the MII Management Interface frame format.
Table 8. MII Management Interface Frame Format
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data Bits [15:0]
Idle
Read
32 1’s
01
10
AAAAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
AAAAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Serial Management Interface (SMI)
The SMI is the KSZ8873MLL/FLL/RLL non-standard MIIM interface that provides access to all KSZ8873MLL/FLL/RLL
configuration registers. This interface allows an external device to completely monitor and control the states of the
KSZ8873MLL/FLL/RLL.
The SMI interface consists of the following:
A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external controller to
communicate with the KSZ8873MLL/FLL/RLL device.
Access to all KSZ8873MLL/FLL/RLL configuration registers. Register access includes the Global, Port and Advanced
Control registers 0-198 (0x00 – 0xC6), and indirect access to the standard MIIM registers [0:5] and custom MIIM
registers [29, 31].
Table 9 depicts the SMI frame format.
Table 9. Serial Management Interface (SMI) Frame Format
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data Bits [15:0]
Idle
Read
32 1’s
01
00
1xRRR
RRRRR
Z0
0000_0000_DDDD_DDDD
Z
Write
32 1’s
01
00
0xRRR
RRRRR
10
xxxx_xxxx_DDDD_DDDD
Z
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register
write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit[3] is
undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write operations.
To access the KSZ8873MLL/FLL/RLL Registers 0-196 (0x00 – 0xC6), the following applies:
PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address; that is, {PHYAD[2:0], REGAD[4:0]} = bits
[7:0] of the 8-bit address.
TA bits [1:0] are ’Z0’ means the processor MDIO pin is changed to input Hi-Z from output mode and the followed ‘0’ is
the read response from device.
TA bits [1:0] are set to ’10’ when write registers.
Registers are 8 data bits wide.
For read operation, data bits [15:8] are read back as 0’s.
For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8873MLL | 功能描述:以太網(wǎng) IC 3-Port Fast Ethernet Switch with 1x MII Interface - Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL AM | 功能描述:以太網(wǎng) IC 3-Port 10/100 Ethernet Switch with 1x MII Interface (Automotive Grade, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL AM TR | 功能描述:以太網(wǎng) IC 3-Port 10/100 Ethernet Switch with 1x MII Interface (Automotive Grade, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL/8863MLL | 制造商:Micrel Inc 功能描述:EVAL BOARD |
| KSZ8873MLL_09 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Integrated 3-Port 10/100 Managed Switch with PHYs |
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