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參數(shù)資料
| 型號(hào)： | KSZ8873FLLI |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 53/115頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ETHERNET SWITCH 3PORT 64LQFP |
| 產(chǎn)品培訓(xùn)模塊： | KSZ8873 Ethernet Switches |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 控制器類(lèi)型： | 以太網(wǎng)開(kāi)關(guān)控制器 |
| 接口： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 576-3632 KSZ8873FLLI-ND |
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Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
42
Revision 1.6
For KSZ8873MLL/FLL/RLL I2C Master configuration, the EEPROM stores the configuration data for Register 0 to
Register 120 (as defined in the KSZ8873MLL/FLL/RLL register map) with the exception of the “Read Only” status
registers. After the de-assertion of reset, the KSZ8873MLL/FLL/RLL sequentially reads in the configuration data for all
control registers, starting from Register 0.
....
RST_N
SCL
SDA
t
prgm<15 ms
Figure 8. EEPROM Configuration Timing Diagram
The following is a sample procedure for programming the KSZ8873MLL/FLL/RLL with a pre-configured EEPROM:
1.
Connect the KSZ8873MLL/FLL/RLL to the EEPROM by joining the SCL and SDA signals of the respective devices.
2.
Enable I
2C master mode by setting the KSZ8873MLL/FLL/RLL strap-in pins, P2LED[1:0] to “00”.
3.
Check to ensure that the KSZ8873MLL/FLL/RLL reset signal input, RSTN, is properly connected to the external reset
source at the board level.
4.
Program the desired configuration data into the EEPROM.
5.
Place the EEPROM on the board and power up the board.
6.
Assert an active-low reset to the RSTN pin of the KSZ8873MLL/FLL/RLL. After reset is de-asserted, the
KSZ8873MLL/FLL/RLL begins reading the configuration data from the EEPROM. The KSZ8873MLL/FLL/RLL checks
that the first byte read from the EEPROM is “88”. If this value is correct, EEPROM configuration continues. If not,
EEPROM configuration access is denied and all other data sent from the EEPROM is ignored by the
KSZ8873MLL/FLL/RLL.
Note: For proper operation, check to ensure that the KSZ8873MLL/FLL/RLL PWRDN input signal is not asserted during
the reset operation. The PWRDN input is active low.
I
2C Slave Serial Bus Configuration
In managed mode, the KSZ8873MLL/FLL/RLL can be configured as an I2C slave device. In this mode, an I2C master
device (external controller/CPU) has complete programming access to the KSZ8873MLL/FLL/RLL’s 198 registers.
Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to
the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table,” and “MIB Counters.” The tables and counters are indirectly
accessed via registers 121 to 131.
In
I
2C slave mode, the KSZ8873MLL/FLL/RLL operates like other I2C slave devices. Addressing the
KSZ8873MLL/FLL/RLL’s 8-bit registers is similar to addressing Atmel’s AT24C02 EEPROM’s memory locations. Details of
I
2C read/write operations and related timing information can be found in the AT24C02 Datasheet.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8873MLL | 功能描述:以太網(wǎng) IC 3-Port Fast Ethernet Switch with 1x MII Interface - Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL AM | 功能描述:以太網(wǎng) IC 3-Port 10/100 Ethernet Switch with 1x MII Interface (Automotive Grade, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL AM TR | 功能描述:以太網(wǎng) IC 3-Port 10/100 Ethernet Switch with 1x MII Interface (Automotive Grade, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL/8863MLL | 制造商:Micrel Inc 功能描述:EVAL BOARD |
| KSZ8873MLL_09 | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:Integrated 3-Port 10/100 Managed Switch with PHYs |
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