參數(shù)資料
型號(hào): KSZ8873FLLI
廠商: Micrel Inc
文件頁(yè)數(shù): 54/115頁(yè)
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
產(chǎn)品培訓(xùn)模塊: KSZ8873 Ethernet Switches
標(biāo)準(zhǔn)包裝: 160
控制器類型: 以太網(wǎng)開(kāi)關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 576-3632
KSZ8873FLLI-ND
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Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
43
Revision 1.6
Two fixed 8-bit device addresses are used to address the KSZ8873MLL/FLL/RLL in I2C slave mode. One is for read; the
other is for write. The addresses are as follow:
1011_1111 <read>
1011_1110 <write>
The following is a sample procedure for programming the KSZ8873MLL/FLL/RLL using the I
2C slave serial bus:
1.
Enable I
2C slave mode by setting the KSZ8873MLL/FLL/RLL strap-in Pins P2LED[1:0] to “01”.
2.
Power up the board and assert reset to the KSZ8873MLL/FLL/RLL. Configure the desired register settings in the
KSZ8873MLL/FLL/RLL, using the I2C write operation.
3.
Read back and verify the register settings in the KSZ8873MLL/FLL/RLL, using the I2C read operation.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down”
can be programmed after the switch has been started.
SPI Slave Serial Bus Configuration
In managed mode, the KSZ8873MLL/FLL/RLL can be configured as a SPI slave device. In this mode, a SPI master
device (external controller/CPU) has complete programming access to the KSZ8873MLL/FLL/RLL’s 198 registers.
Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to
the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are indirectly
accessed via registers 121 to 131.
The KSZ8873MLL/FLL/RLL supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data
write. SPI multiple read and multiple write are also supported by the KSZ8873MLL/FLL/RLL to expedite register read back
and register configuration, respectively.
SPI multiple read is initiated when the master device continues to drive the KSZ8873MLL/FLL/RLL SPISN input pin (SPI
Slave Select signal) low after a byte (a register) is read. The KSZ8873MLL/FLL/RLL internal address counter increments
automatically to the next byte (next register) after the read. The next byte at the next register address is shifted out onto
the KSZ8873MLL/FLL/RLL SPIQ output pin. SPI multiple read continues until the SPI master device terminates it by de-
asserting the SPISN signal to the KSZ8873MLL/FLL/RLL.
Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8873MLL/FLL/RLL SPISN input
pin low after a byte (a register) is written. The KSZ8873MLL/FLL/RLL internal address counter increments automatically to
the next byte (next register) after the write. The next byte that is sent from the master device to the KSZ8873MLL/FLL/RLL
SDA input pin is written to the next register address. SPI multiple write continues until the SPI master device terminates it
by de-asserting the SPISN signal to the KSZ8873MLL/FLL/RLL.
For both SPI multiple read and multiple write, the KSZ8873MLL/FLL/RLL internal address counter wraps back to register
address zero once the highest register address is reached. This feature allows all 198 KSZ8873MLL/FLL/RLL registers to
be read, or written with a single SPI command from any initial register address.
The KSZ8873MLL/FLL/RLL is capable of supporting a SPI bus.
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