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參數(shù)資料
| 型號(hào)： | KSZ8873FLLI |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 27/115頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET SWITCH 3PORT 64LQFP |
| 產(chǎn)品培訓(xùn)模塊： | KSZ8873 Ethernet Switches |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 控制器類型： | 以太網(wǎng)開(kāi)關(guān)控制器 |
| 接口： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤(pán) |
| 其它名稱： | 576-3632 KSZ8873FLLI-ND |
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Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
19
Revision 1.6
Functional Description
The KSZ8873MLL/FLL/RLL contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer
2 managed switch.
The KSZ8873MLL/FLL/RLL has the flexibility to reside in either a managed or unmanaged design. In a managed design,
the host processor has complete control of the KSZ8873MLL/FLL/RLL via the SMI interface, MIIM interface, SPI bus, or
I
2C bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.
On the media side, the KSZ8873MLL/FLL/RLL supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the
design more efficient and allow for lower power consumption and smaller chip die size.
Functional Overview: Physical Layer Transceiver
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an
external1% 11.8K
resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
100BASE-TX Transmit
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8873MLL/FLL/RLL generates 125MHz, 62.5MHz, and 31.25MHz clocks for system timing. Internal clocks are
generated from an external 25MHz or 50MHz crystal or oscillator. KSZ8873RLL can generate a 50MHz reference clock
for the RMII interface.
Scrambler/De-Scrambler (100BASE-TX Only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register
(LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming
data stream using the same sequence as at the transmitter.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8873MLL | 功能描述:以太網(wǎng) IC 3-Port Fast Ethernet Switch with 1x MII Interface - Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL AM | 功能描述:以太網(wǎng) IC 3-Port 10/100 Ethernet Switch with 1x MII Interface (Automotive Grade, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL AM TR | 功能描述:以太網(wǎng) IC 3-Port 10/100 Ethernet Switch with 1x MII Interface (Automotive Grade, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL/8863MLL | 制造商:Micrel Inc 功能描述:EVAL BOARD |
| KSZ8873MLL_09 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Integrated 3-Port 10/100 Managed Switch with PHYs |
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